| Message ID | 20231121-topic-sm8650-upstream-dt-v3-0-db9d0507ffd3@linaro.org |
|---|---|
| Headers | show |
| Series | arm64: dts: qcom: Introduce SM8650 platforms device tree | expand |
> + > + usb_1: usb@a6f8800 { > + compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; > + reg = <0 0x0a6f8800 0 0x400>; > + > + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 15 IRQ_TYPE_EDGE_RISING>, > + <&pdc 14 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "hs_phy_irq", Hi Neil, This GIC_SPI 130 is actually pwr_event IRQ, not hs_phy_irq. > + "ss_phy_irq", > + "dm_hs_phy_irq", > + "dp_hs_phy_irq"; > + Regards, Krishna,
On 22/11/2023 09:07, Krishna Kurapati PSSNV wrote: >> + >> + usb_1: usb@a6f8800 { >> + compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; >> + reg = <0 0x0a6f8800 0 0x400>; >> + >> + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, >> + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, >> + <&pdc 15 IRQ_TYPE_EDGE_RISING>, >> + <&pdc 14 IRQ_TYPE_EDGE_RISING>; >> + interrupt-names = "hs_phy_irq", > > Hi Neil, > > This GIC_SPI 130 is actually pwr_event IRQ, not hs_phy_irq. Thanks, Will fix in v4 Neil > >> + "ss_phy_irq", >> + "dm_hs_phy_irq", >> + "dp_hs_phy_irq"; >> + > > Regards, > Krishna,
This introduces the Device Tree for the recently announced Snapdragon 8 Gen 3 from Qualcomm, you can find the marketing specifications at: https://docs.qualcomm.com/bundle/publicresource/87-71408-1_REV_B_Snapdragon_8_gen_3_Mobile_Platform_Product_Brief.pdf Bindings and base Device Tree for the SM8650 SoC, MTP (Mobile Test Platform) and QRD (Qualcommm Reference Device) are splited in two: - 1-5: boot-to-shell first set that are only build-dependent on Clock bindings - 6-8: multimedia second set that are build-dependent with Interconnect bindings Features added and enabled: - CPUs with CPUFREQ, SCPI idle states - QICv3, IOMMU, Timers - Interconnect NoCs with LLCC/CPU BWMONs - SoC 3xTemperature Sensors - Pinctrl/GPIO with PDC wakeup support - Global, GPU, Display, TCSR Clock Controllers - cDSP, aDSP and MPSS with SMP2P - QuP/I2C Master Hub I2C and SPI controllers + GPI DMA - PCIe 0/1 - USB2/USB3 with USB3/DP Combo PHY - UFS with Inline Crypto Engine - Crypto Engine + DMA and True Random Generator - SDHCI - Mobile Display Subsystem with 2xDSI output - PMIC Glink (USB-PD UCSI + Altmode) provided by aDSP firmware - GPIO and PMIC Buttons/LEDs on QRD board - WCN7850 Bluetooth - DSI + Touch panel Bindings Dependencies: - aoss-qmp: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-aoss-qmp-v1-1-8940621d704c@linaro.org/ - Reviewed - bwmon: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-bwmon-v1-1-11efcdd8799e@linaro.org/ - Reviewed - cpufreq: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-cpufreq-v1-1-31dec4887d14@linaro.org/ - Applied - dwc3: https://lore.kernel.org/all/20231030-topic-sm8650-upstream-bindings-dwc3-v2-1-60c0824fb835@linaro.org/ - Reviewed - gpi: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-gpi-v2-1-4de85293d730@linaro.org/ - Reviewed - ice: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-ice-v1-1-6b2bc14e71db@linaro.org/ - Applied - ipcc: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-ipcc-v1-1-acca4318d06e@linaro.org/ - Reviewed - pcie: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-pcie-v1-1-0e3d6f0c5827@linaro.org/ - Reviewed - pcd: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-pdc-v1-1-42f62cc9858c@linaro.org/ - Reviewed - pmic-glink: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-pmic-glink-v1-1-0c2829a62565@linaro.org/ - Reviewed - qce: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-qce-v1-1-7e30dba20dbf@linaro.org/ - Applied - rng: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-rng-v1-1-6b6a020e3441@linaro.org/ - Applied - scm: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-scm-v2-1-68a8db7ae434@linaro.org/ - Reviewed - sdhci: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-scm-v2-1-68a8db7ae434@linaro.org/ - Applied - smmu: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-smmu-v1-1-bfa25faa061e@linaro.org/ - Reviewed - tsens: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-tsens-v2-1-5add2ac04943@linaro.org/ - Reviewed - ufs: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-bindings-ufs-v3-1-a96364463fd5@linaro.org - Applied - clocks: https://lore.kernel.org/all/20231106-topic-sm8650-upstream-clocks-v3-0-761a6fadb4c0@linaro.org/ - interconnect: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-interconnect-v1-0-b7277e03aa3d@linaro.org/ - Reviewed - llcc: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-llcc-v2-0-f281cec608e2@linaro.org - Reviewed - mdss: https://lore.kernel.org/all/20231030-topic-sm8650-upstream-mdss-v2-0-43f1887c82b8@linaro.org/ - Reviewed - phy: https://lore.kernel.org/all/20231030-topic-sm8650-upstream-phy-v2-0-a543a4c4b491@linaro.org/ - Applied - remoteproc: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-remoteproc-v2-0-609ee572e0a2@linaro.org - rpmpd: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-rpmpd-v1-0-f25d313104c6@linaro.org/ - Applied - tlmm: https://lore.kernel.org/all/20231106-topic-sm8650-upstream-tlmm-v3-0-0e179c368933@linaro.org/ - Applied - goodix: https://lore.kernel.org/all/20231106-topic-goodix-berlin-upstream-initial-v11-0-5c47e9707c03@linaro.org/ - Reviewed Build Dependencies: - clocks: https://lore.kernel.org/all/20231106-topic-sm8650-upstream-clocks-v3-0-761a6fadb4c0@linaro.org/ - interconnect: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-interconnect-v1-0-b7277e03aa3d@linaro.org/ - Reviewed Other: - socinfo: https://lore.kernel.org/all/20231030-topic-sm8650-upstream-socinfo-v2-0-4751e7391dc9@linaro.org/ - Reviewed - defconfig: https://lore.kernel.org/all/20231121-topic-sm8650-upstream-defconfig-v1-1-2500565fc21b@linaro.org/ Merge Strategy: - Merge patches 1-5 with Clock bindings immutable branch - Merge patches 6-8 with Interconnect immutable branch For convenience, a regularly refreshed linux-next based git tree containing all the SM8650 related work is available at: https://git.codelinaro.org/neil.armstrong/linux/-/tree/topic/sm8650/upstream/integ Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- Changes in v3: - Cleanup of thermal zones - Rename SDE pinctrl to real signal names - Link to v2: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-dt-v2-0-44d6f9710fa7@linaro.org Changes in v2: - Drop RFC since most of bindings were reviewed - Collect Reviewed-by/Acked-bys - Remove #ifndef PMK8550VE_SID in favor of #define in sm8550 dts - Add allow-set-load/allowed-modes to LDOs - Add QCOM_ICC_TAG_ALWAYS/QCOM_ICC_TAG_ACTIVE_ONLY to interconnects = <> instead of 0 & 3 - minimal sm8650-qrd.dts cleanup - Link to v1: https://lore.kernel.org/r/20231025-topic-sm8650-upstream-dt-v1-0-a821712af62f@linaro.org --- Neil Armstrong (8): dt-bindings: arm: qcom: document SM8650 and the reference boards arm64: dts: qcom: add initial SM8650 dtsi arm64: dts: qcom: pm8550ve: make PMK8550VE SID configurable arm64: dts: qcom: sm8650: add initial SM8650 MTP dts arm64: dts: qcom: sm8650: add initial SM8650 QRD dts arm64: dts: qcom: sm8650: add interconnect dependent device nodes arm64: dts: qcom: sm8650-mtp: add interconnect dependent device nodes arm64: dts: qcom: sm8650-qrd: add interconnect dependent device nodes Documentation/devicetree/bindings/arm/qcom.yaml | 7 + arch/arm64/boot/dts/qcom/Makefile | 2 + arch/arm64/boot/dts/qcom/pm8550ve.dtsi | 6 +- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 1 + arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 1 + arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 678 +++ arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 803 ++++ arch/arm64/boot/dts/qcom/sm8650.dtsi | 5382 +++++++++++++++++++++++ 8 files changed, 6877 insertions(+), 3 deletions(-) --- base-commit: 07b677953b9dca02928be323e2db853511305fa9 change-id: 20231016-topic-sm8650-upstream-dt-ee696999df62 Best regards,