| Message ID | 20240626143302.810632-1-quic_devipriy@quicinc.com |
|---|---|
| Headers | show |
| Series | Add NSS clock controller support for IPQ9574 | expand |
On 26.06.2024 4:33 PM, Devi Priya wrote: > Add a node for the nss clock controller found on ipq9574 based devices. > > Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> > --- Title: s/support for// You're adding the node, not the support for it. The nodes look good. Looking at the driver, the interconnect paths that will be sync_state'd away due to no consumers don't seem to be super critical for the system, so I'm assuming this doesn't crash So, with the title fixed: Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad
On 6/26/2024 11:44 PM, Dmitry Baryshkov wrote: > On Wed, Jun 26, 2024 at 08:03:02PM GMT, Devi Priya wrote: >> NSSCC driver is needed to enable the ethernet interfaces and not >> necessary for the bootup of the SoC, hence build it as a module. > > It is used on this-and-that device. > Hi Dmitry, Sorry for the delayed response. NSSCC driver is needed to enable the ethernet interfaces present in RDP433 based on IPQ9574. Since this is not necessary for bootup enabling it as a module. Thanks & Regards, Manikanta. >> >> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> >> --- >> Changes in V5: >> - No change >> >> arch/arm64/configs/defconfig | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig >> index dfaec2d4052c..40a5ea212518 100644 >> --- a/arch/arm64/configs/defconfig >> +++ b/arch/arm64/configs/defconfig >> @@ -1300,6 +1300,7 @@ CONFIG_IPQ_GCC_5332=y >> CONFIG_IPQ_GCC_6018=y >> CONFIG_IPQ_GCC_8074=y >> CONFIG_IPQ_GCC_9574=y >> +CONFIG_IPQ_NSSCC_9574=m >> CONFIG_MSM_GCC_8916=y >> CONFIG_MSM_MMCC_8994=m >> CONFIG_MSM_GCC_8994=y >> -- >> 2.34.1 >> >
On 6/29/2024 7:00 PM, Konrad Dybcio wrote: > On 26.06.2024 4:33 PM, Devi Priya wrote: >> Add a node for the nss clock controller found on ipq9574 based devices. >> >> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> >> --- > > Title: s/support for// > > You're adding the node, not the support for it. > > The nodes look good. Looking at the driver, the interconnect paths that will > be sync_state'd away due to no consumers don't seem to be super critical for > the system, so I'm assuming this doesn't crash > > So, with the title fixed: > Hi Konrad, Sorry for the delayed response. Okay, sure. Will fix the title. Thanks & Regards, Manikanta.
On 6/26/2024 11:43 PM, Dmitry Baryshkov wrote: > On Wed, Jun 26, 2024 at 08:03:01PM GMT, Devi Priya wrote: >> Add a node for the nss clock controller found on ipq9574 based devices. >> >> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> >> --- >> Changes in V5: >> - Dropped interconnects from nsscc node and added >> interconnect-cells to NSS clock provider so that it can be used >> as icc provider. >> >> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 41 +++++++++++++++++++++++++++ >> 1 file changed, 41 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> index 48dfafea46a7..b6f8800bf63c 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> @@ -11,6 +11,8 @@ >> #include <dt-bindings/interconnect/qcom,ipq9574.h> >> #include <dt-bindings/interrupt-controller/arm-gic.h> >> #include <dt-bindings/reset/qcom,ipq9574-gcc.h> >> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h> >> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h> >> #include <dt-bindings/thermal/thermal.h> >> >> / { >> @@ -19,6 +21,24 @@ / { >> #size-cells = <2>; >> >> clocks { >> + bias_pll_cc_clk: bias-pll-cc-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <1200000000>; >> + #clock-cells = <0>; >> + }; >> + >> + bias_pll_nss_noc_clk: bias-pll-nss-noc-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <461500000>; >> + #clock-cells = <0>; >> + }; >> + >> + bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <353000000>; >> + #clock-cells = <0>; >> + }; > > What is the source for these clocks? Is it really an on-board crystal? > Hi Dmitry, Sorry for the delayed response. No, the CMN PLL [1] is the source for these clocks. Will remove these nodes and set these entries to 0 in the nsscc node until the CMN PLL driver posted with these clocks. 1: https://lore.kernel.org/lkml/20240827-qcom_ipq_cmnpll-v3-0-8e009cece8b2@quicinc.com/ Thanks & Regards, Manikanta.
On 10/6/2024 10:13 PM, Dmitry Baryshkov wrote: > On Fri, Oct 04, 2024 at 01:26:27PM GMT, Manikanta Mylavarapu wrote: >> >> >> On 6/26/2024 11:44 PM, Dmitry Baryshkov wrote: >>> On Wed, Jun 26, 2024 at 08:03:02PM GMT, Devi Priya wrote: >>>> NSSCC driver is needed to enable the ethernet interfaces and not >>>> necessary for the bootup of the SoC, hence build it as a module. >>> >>> It is used on this-and-that device. >>> >> >> Hi Dmitry, >> >> Sorry for the delayed response. >> >> NSSCC driver is needed to enable the ethernet interfaces present >> in RDP433 based on IPQ9574. Since this is not necessary for bootup >> enabling it as a module. > > Commit message, please. > Hi Dmitry, Okay, sure. Thanks & Regards, Manikanta.