| Message ID | 20241014-add_display_support_for_qcs615-v1-0-4efa191dbdd4@quicinc.com |
|---|---|
| Headers | show |
| Series | add_display_support_for_QCS615 | expand |
On Mon, Oct 14, 2024 at 05:47:28PM +0800, fangez via B4 Relay wrote: > From: lliu6 <quic_lliu6@quicinc.com> This is not a name. > > Add display mdss and dsi configuration for QCS615 SoC. MDSS, DSI separate Ride configuration to a separate commit Patch order is wrong. - dt-bindings - driver changes - dtsi - dts > > Signed-off-by: lliu6 <quic_lliu6@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcs615-ride.dts | 101 ++++++++++++++++ > arch/arm64/boot/dts/qcom/qcs615.dtsi | 195 +++++++++++++++++++++++++++++++ > 2 files changed, 296 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts > index d05a881d7ffeca9de175af2a9062f5bccadcbdfd..f275145c395aedb71bdcd8a88b82917db53e7167 100644 > --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts > +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts > @@ -207,6 +207,107 @@ &gcc { > <&sleep_clk>; > }; > > +&i2c2 { > + clock-frequency = <400000>; > + pinctrl-0 = <&qup_i2c2_data_clk &ioexp_intr_active &ioexp_reset_active>; > + pinctrl-names = "default"; > + status = "okay"; empty line > + ioexp: gpio@3e { > + #gpio-cells = <2>; > + #interrupt-cells = <2>; > + compatible = "semtech,sx1509q"; > + reg = <0x3e>; > + interrupt-parent = <&tlmm>; > + interrupts = <58 0>; > + gpio-controller; > + interrupt-controller; > + semtech,probe-reset; > + pinctrl-names = "default"; > + pinctrl-0 = <&dsi0_hpd_cfg_pins &dsi0_cdet_cfg_pins &dp_hpd_cfg_pins>; No, these pins are not used by the IO expander. Please moved them to the corresponding devices. empty line > + dsi0_hpd_cfg_pins: gpio0-cfg { What exactly is DSI HPD? > + pins = "gpio0"; > + bias-pull-up; > + }; and here (and you'll guess all other relevant places, I hope it's obvious). > + dsi0_cdet_cfg_pins: gpio1-cfg { > + pins = "gpio1"; > + bias-pull-down; > + }; > + dp_hpd_cfg_pins: gpio8-cfg { > + pins = "gpio8"; > + bias-pull-down; > + }; > + }; > + > + i2c-mux@77 { > + compatible = "nxp,pca9542"; > + reg = <0x77>; > + #address-cells = <1>; > + #size-cells = <0>; > + i2c@0 { > + reg = <0>; > + #address-cells = <1>; > + #size-cells = <0>; > + anx_7625_1: anx7625@2c { Are there more than one? > + compatible = "analogix,anx7625"; > + reg = <0x58>; > + interrupt-parent = <&ioexp>; > + interrupts = <0 0>; > + enable-gpios = <&tlmm 4 0>; Use defines for the GPIO flags instead of 0 > + reset-gpios = <&tlmm 5 0>; > + wakeup-source; > + }; > + }; > + }; > +}; > + > +&anx_7625_1 { No need to, keep it in the same node. > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + port@0 { > + reg = <0>; > + anx_7625_1_in: endpoint { > + remote-endpoint = <&mdss_dsi0_out>; > + }; > + }; Missing port@1 and the connector node. > + }; > +}; > + > +&mdss { > + status = "okay"; > +}; > + > +&mdss_dsi0 { > + status = "okay"; Status is the last property. > + vdda-supply = <&vreg_l11a>; > +}; > + > +&mdss_dsi0_out { > + remote-endpoint = <&anx_7625_1_in>; > + data-lanes = <0 1 2 3>; > +}; > + > +&mdss_dsi0_phy { > + status = "okay"; > + vdds-supply = <&vreg_l5a>; > +}; > + > +&tlmm { > + ioexp_intr_active: ioexp_intr_active { This doesn't seem to be validated. Please check your patches before sending. > + pins = "gpio58"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + ioexp_reset_active: ioexp_reset_active { > + pins = "gpio3"; > + function = "gpio"; > + drive-strength = <2>; > + bias-disable; > + output-high; > + }; > +}; > + > &qupv3_id_0 { > status = "okay"; > }; > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi > index 8e2199bb180d85a86a882c4253778c7e8f34798b..2a6c08220e6c4ded49861754d81d0924389dd93e 100644 > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi > @@ -1266,6 +1266,201 @@ camcc: clock-controller@ad00000 { > #power-domain-cells = <1>; > }; > > + mdss: display-subsystem@ae00000 { > + compatible = "qcom,qcs615-mdss"; > + reg = <0 0x0ae00000 0 0x1000>; > + reg-names = "mdss"; > + > + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, QCOM_ICC_TAG_ALWAYS > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; > + interconnect-names = "mdp0-mem", > + "cpu-cfg"; > + > + power-domains = <&dispcc MDSS_CORE_GDSC>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>; > + > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + iommus = <&apps_smmu 0x800 0x0>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + status = "disabled"; > + > + mdss_mdp: display-controller@ae01000 { > + compatible = "qcom,qcs615-dpu"; > + reg = <0 0x0ae01000 0 0x8f000>, > + <0 0x0aeb0000 0 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; Please indent lists so that the values are one under another, starting at the same column. > + clock-names = "bus", > + "iface", > + "lut", > + "core", > + "vsync"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <19200000>; > + > + operating-points-v2 = <&mdp_opp_table>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dpu_intf0_out: endpoint { > + }; > + }; > + > + port@1 { > + reg = <1>; > + dpu_intf1_out: endpoint { > + remote-endpoint = <&mdss_dsi0_in>; > + }; > + }; > + }; > + > + mdp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-375000000 { > + opp-hz = /bits/ 64 <375000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-500000000 { > + opp-hz = /bits/ 64 <500000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + > + opp-575000000 { > + opp-hz = /bits/ 64 <575000000>; > + required-opps = <&rpmhpd_opp_turbo>; > + }; > + > + opp-650000000 { > + opp-hz = /bits/ 64 <650000000>; > + required-opps = <&rpmhpd_opp_turbo_l1>; > + }; > + }; > + }; > + > + mdss_dsi0: dsi@ae94000 { > + compatible = "qcom,qcs615-dsi-ctrl", "qcom,mdss-dsi-ctrl"; > + reg = <0 0x0ae94000 0 0x400>; > + reg-names = "dsi_ctrl"; > + > + interrupt-parent = <&mdss>; > + interrupts = <4>; > + > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, > + <&dispcc DISP_CC_MDSS_ESC0_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>; > + clock-names = "byte", > + "byte_intf", > + "pixel", > + "core", > + "iface", > + "bus"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; > + assigned-clock-parents = <&mdss_dsi0_phy 0>, > + <&mdss_dsi0_phy 1>; > + > + operating-points-v2 = <&dsi0_opp_table>; > + > + phys = <&mdss_dsi0_phy>; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + > + dsi0_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-164000000 { > + opp-hz = /bits/ 64 <164000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-187500000 { > + opp-hz = /bits/ 64 <187500000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-225000000 { > + opp-hz = /bits/ 64 <225000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-262500000 { > + opp-hz = /bits/ 64 <262500000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + mdss_dsi0_in: endpoint { > + remote-endpoint = <&dpu_intf1_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + mdss_dsi0_out: endpoint { > + }; > + }; > + }; > + }; > + > + mdss_dsi0_phy: phy@ae94400 { > + compatible = "qcom,qcs615-dsi-phy-14nm"; > + reg = <0 0x0ae94400 0 0x100>, > + <0 0x0ae94500 0 0x300>, > + <0 0x0ae94800 0 0x188>; > + reg-names = "dsi_phy", > + "dsi_phy_lane", > + "dsi_pll"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "iface", "ref"; > + > + status = "disabled"; > + }; Does QCS615 have a DP controller? Please mention it in the commit message. > + }; > + > dispcc: clock-controller@af00000 { > compatible = "qcom,qcs615-dispcc"; > reg = <0 0xaf00000 0 0x20000>; > > -- > 2.25.1 > >
On Mon, Oct 14, 2024 at 05:47:31PM +0800, fangez via B4 Relay wrote: > From: lliu6 <quic_lliu6@quicinc.com> > > Add bindings for the display hardware on QCS615. > > Signed-off-by: lliu6 <quic_lliu6@quicinc.com> > --- > .../bindings/display/msm/qcom,qcs615-dpu.yaml | 117 +++++++++ > .../bindings/display/msm/qcom,qcs615-mdss.yaml | 278 +++++++++++++++++++++ > 2 files changed, 395 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcs615-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcs615-dpu.yaml > new file mode 100644 > index 0000000000000000000000000000000000000000..35339092cb4f905541a7f70f42166bd0b0b7dee7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcs615-dpu.yaml > @@ -0,0 +1,117 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/msm/qcom,qcs615-dpu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm QCS615 Display DPU > + > +maintainers: > + - lliu6 <quic_lliu6@quicinc.com> No, you are not. Please at least list Abhinav and me. > + > +$ref: /schemas/display/msm/dpu-common.yaml# > + > +properties: > + compatible: > + const: qcom,qcs615-dpu > + > + reg: > + items: > + - description: Address offset and size for mdp register set > + - description: Address offset and size for vbif register set > + > + reg-names: > + items: > + - const: mdp > + - const: vbif > + > + clocks: > + items: > + - description: Display ahb clock > + - description: Display hf axi clock > + - description: Display core clock > + - description: Display vsync clock > + > + clock-names: > + items: > + - const: iface > + - const: bus > + - const: core > + - const: vsync > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,qcs615-dispcc.h> I can not pick this up, these headers are not present in the msm-next tree. Please use ephemeral nodes instead. > + #include <dt-bindings/clock/qcom,qcs615-gcc.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h> > + #include <dt-bindings/interconnect/qcom,icc.h> > + #include <dt-bindings/power/qcom-rpmpd.h> > + > + display-controller@ae01000 { > + compatible = "qcom,qcs615-dpu"; > + reg = <0x0ae01000 0x8f000>, > + <0x0aeb0000 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "iface", "bus", "lut" "core", "vsync"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <19200000>; > + > + operating-points-v2 = <&mdp_opp_table>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dpu_intf0_out: endpoint { > + }; > + }; Indentation is definitely wrong. > + > + port@1 { > + reg = <1>; > + dpu_intf1_out: endpoint { > + remote-endpoint = <&mdss_dsi0_in>; > + }; > + }; > + > + }; > + > + mdp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-375000000 { > + opp-hz = /bits/ 64 <375000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-500000000 { > + opp-hz = /bits/ 64 <500000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + > + opp-575000000 { > + opp-hz = /bits/ 64 <575000000>; > + required-opps = <&rpmhpd_opp_turbo>; > + }; > + > + opp-650000000 { > + opp-hz = /bits/ 64 <650000000>; > + required-opps = <&rpmhpd_opp_turbo_l1>; > + }; > + }; > + }; > +... > diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcs615-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcs615-mdss.yaml > new file mode 100644 > index 0000000000000000000000000000000000000000..fdad15c358892306dcb2c1b78319934c504cfc2b > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcs615-mdss.yaml > @@ -0,0 +1,278 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/msm/qcom,qcs615-mdss.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm QCS615 Display MDSS > + > +maintainers: > + - lliu6 <quic_lliu6@quicinc.com> > + > +description: > + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates > + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree > + bindings of MDSS are mentioned for QCS615 target. > + > +$ref: /schemas/display/msm/mdss-common.yaml# > + > +properties: > + compatible: > + items: > + - const: qcom,qcs615-mdss > + > + clocks: > + items: > + - description: Display AHB clock from gcc > + - description: Display hf axi clock > + - description: Display sf axi clock > + - description: Display core clock > + > + clock-names: > + items: > + - const: iface > + - const: bus > + - const: nrt_bus > + - const: core > + > + iommus: > + maxItems: 1 > + > + interconnects: > + maxItems: 2 > + > + interconnect-names: > + maxItems: 2 > + > +patternProperties: > + "^display-controller@[0-9a-f]+$": > + type: object > + additionalProperties: true > + > + properties: > + compatible: > + const: qcom,qcs615-dpu > + > + "^displayport-controller@[0-9a-f]+$": > + type: object > + additionalProperties: true > + > + properties: > + compatible: > + contains: > + const: qcom,qcs615-dp It is not described anywhere, isn't it? > + > + "^dsi@[0-9a-f]+$": > + type: object > + additionalProperties: true > + No empty line > + properties: > + compatible: > + items: > + - const: qcom,qcs615-dsi-ctrl > + - const: qcom,mdss-dsi-ctrl > + > + "^phy@[0-9a-f]+$": > + type: object > + additionalProperties: true > + No empty line > + properties: > + compatible: > + const: qcom,qcs615-dsi-phy-14nm > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,qcs615-dispcc.h> > + #include <dt-bindings/clock/qcom,qcs615-gcc.h> Same comment, use ephemeral nodes instead of listing the clocks exactly. > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h> > + #include <dt-bindings/interconnect/qcom,icc.h> > + #include <dt-bindings/power/qcom-rpmpd.h> > + > + display-subsystem@ae00000 { > + compatible = "qcom,qcs615-mdss"; > + reg = <0x0ae00000 0x1000>; > + reg-names = "mdss"; > + > + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; > + interconnect-names = "mdp0-mem", "cpu-cfg"; Wrong indentation. No tabs in yaml files. Did it even compile? > + > + power-domains = <&dispcc MDSS_CORE_GDSC>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>; > + > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + iommus = <&apps_smmu 0x800 0x0>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + display-controller@ae01000 { > + compatible = "qcom,qcs615-dpu"; > + reg = <0x0ae01000 0x8f000>, > + <0x0aeb0000 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "iface", "bus", "lut", "core", "vsync"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <19200000>; > + > + operating-points-v2 = <&mdp_opp_table>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dpu_intf0_out: endpoint { > + }; > + }; > + > + port@1 { > + reg = <1>; > + dpu_intf1_out: endpoint { > + remote-endpoint = <&mdss_dsi0_in>; > + }; > + }; > + > + }; > + > + mdp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-375000000 { > + opp-hz = /bits/ 64 <375000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-500000000 { > + opp-hz = /bits/ 64 <500000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + > + opp-575000000 { > + opp-hz = /bits/ 64 <575000000>; > + required-opps = <&rpmhpd_opp_turbo>; > + }; > + > + opp-650000000 { > + opp-hz = /bits/ 64 <650000000>; > + required-opps = <&rpmhpd_opp_turbo_l1>; > + }; > + }; > + }; > + > + dsi@ae94000 { > + compatible = "qcom,qcs615-dsi-ctrl", "qcom,mdss-dsi-ctrl"; > + reg = <0x0ae94000 0x400>; > + reg-names = "dsi_ctrl"; > + > + interrupt-parent = <&mdss>; > + interrupts = <4>; > + > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, > + <&dispcc DISP_CC_MDSS_ESC0_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>; > + clock-names = "byte", > + "byte_intf", > + "pixel", > + "core", > + "iface", > + "bus"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; > + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; > + > + operating-points-v2 = <&dsi0_opp_table>; > + > + phys = <&mdss_dsi0_phy>; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + mdss_dsi0_in: endpoint { > + remote-endpoint = <&dpu_intf1_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + mdss_dsi0_out: endpoint { > + }; > + }; > + }; > + > + dsi0_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-164000000 { > + opp-hz = /bits/ 64 <164000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-187500000 { > + opp-hz = /bits/ 64 <187500000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-225000000 { > + opp-hz = /bits/ 64 <225000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-262500000 { > + opp-hz = /bits/ 64 <262500000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > + > + mdss_dsi0_phy: phy@ae94400 { > + compatible = "qcom,qcs615-dsi-phy-14nm"; > + reg = <0x0ae94400 0x100>, > + <0x0ae94500 0x300>, > + <0x0ae94800 0x188>; > + reg-names = "dsi_phy", > + "dsi_phy_lane", > + "dsi_pll"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "iface", "ref"; > + vdds-supply = <&vreg_dsi_phy>; > + }; > + }; > +... > > -- > 2.25.1 > >
On Mon, Oct 14, 2024 at 05:47:27PM +0800, fangez via B4 Relay wrote: > From: lliu6 <quic_lliu6@quicinc.com> > > Enable SX150X pinctrl driver. > > Signed-off-by: lliu6 <quic_lliu6@quicinc.com> Ok, even worse. fangez, you are not the author of the patches, so there is a missing S-o-B. > --- > arch/arm64/configs/defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig > index 76f3a6ee93e979e9e39cb0283699a2753b0dddf4..13ff005ebe0e9cfcf171b08add24465d0ab94f05 100644 > --- a/arch/arm64/configs/defconfig > +++ b/arch/arm64/configs/defconfig > @@ -630,6 +630,7 @@ CONFIG_PINCTRL_SM8350=y > CONFIG_PINCTRL_SM8450=y > CONFIG_PINCTRL_SM8550=y > CONFIG_PINCTRL_SM8650=y > +CONFIG_PINCTRL_SX150X=y > CONFIG_PINCTRL_X1E80100=y > CONFIG_PINCTRL_QCOM_SPMI_PMIC=y > CONFIG_PINCTRL_LPASS_LPI=m > > -- > 2.25.1 > >
On Mon, Oct 14, 2024 at 01:36:52PM +0300, Dmitry Baryshkov wrote: > On Mon, Oct 14, 2024 at 05:47:26PM +0800, fangez via B4 Relay wrote: > > Signed-off-by: fangez <quic_fangez@quicinc.com> > > You didn't copy any of corresponding maintainers or mailing lists, so > most likely your patches will be ignored. Please use b4 tool for > preparing and sending patches. > Ok, you are using b4, excuse me. Then it makes me wonder, how and why you ignored all B4 recommendations and pleads to get required To/Cc lists. > > --- > > lliu6 (6): > > arm64: defconfig: Enable SX150X > > arm64: dts: qcom: qcs615: Add display mdss and dsi configuration > > drm/msm/dpu: Add QCS615 support > > dt-bindings: display/msm: Add QCS615 DSI phy > > dt-bindings: display/msm: Add QCS615 MDSS & DPU > > dt-bindings: display/msm: dsi-controller-main: Document QCS615 > > > > .../bindings/display/msm/dsi-controller-main.yaml | 1 + > > .../bindings/display/msm/dsi-phy-14nm.yaml | 1 + > > .../bindings/display/msm/qcom,qcs615-dpu.yaml | 117 +++++++++ > > .../bindings/display/msm/qcom,qcs615-mdss.yaml | 278 +++++++++++++++++++++ > > arch/arm64/boot/dts/qcom/qcs615-ride.dts | 101 ++++++++ > > arch/arm64/boot/dts/qcom/qcs615.dtsi | 195 +++++++++++++++ > > arch/arm64/configs/defconfig | 1 + > > .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h | 268 ++++++++++++++++++++ > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + > > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + > > drivers/gpu/drm/msm/dsi/dsi_cfg.c | 17 ++ > > drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + > > drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 + > > drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + > > drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 21 ++ > > drivers/gpu/drm/msm/msm_mdss.c | 7 + > > 17 files changed, 1014 insertions(+) > > --- > > base-commit: 77dca4e0530173cb10896cc113f14e6403f0a31a > > change-id: 20241014-add_display_support_for_qcs615-b17bc0d4118e > > > > Best regards, > > -- > > fangez <quic_fangez@quicinc.com> > > > > > > -- > With best wishes > Dmitry
On 14/10/2024 11:47, fangez via B4 Relay wrote: > From: lliu6 <quic_lliu6@quicinc.com> > > QCS615 platform uses the 14nm DSI PHY driver. This patchset is not ready for submission. Please perform first internal review. Please run scripts/checkpatch.pl and fix reported warnings. Then please run `scripts/checkpatch.pl --strict` and (probably) fix more warnings. Some warnings can be ignored, especially from --strict run, but the code here looks like it needs a fix. Feel free to get in touch if the warning is not clear. <form letter> Please use scripts/get_maintainers.pl to get a list of necessary people and lists to CC. It might happen, that command when run on an older kernel, gives you outdated entries. Therefore please be sure you base your patches on recent Linux kernel. Tools like b4 or scripts/get_maintainer.pl provide you proper list of people, so fix your workflow. Tools might also fail if you work on some ancient tree (don't, instead use mainline) or work on fork of kernel (don't, instead use mainline). Just use b4 and everything should be fine, although remember about `b4 prep --auto-to-cc` if you added new patches to the patchset. You missed at least devicetree list (maybe more), so this won't be tested by automated tooling. Performing review on untested code might be a waste of time. Please kindly resend and include all necessary To/Cc entries. </form letter> > > Signed-off-by: lliu6 <quic_lliu6@quicinc.com> > --- > Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml > index 52bbe132e6dae57246200757767edcd1c8ec2d77..029606d9e87e3b184bd10bd4a5076d6923d60e9e 100644 > --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml > +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml > @@ -20,6 +20,7 @@ properties: > - qcom,dsi-phy-14nm-660 > - qcom,dsi-phy-14nm-8953 > - qcom,sm6125-dsi-phy-14nm > + - qcom,qcs615-dsi-phy-14nm Keep the order. Best regards, Krzysztof
On Mon, 14 Oct 2024 at 14:50, fange zhang (QUIC) <quic_fangez@quicinc.com> wrote: > > Dear maintainers, > > Sorry, Please ignore this email thread. We will review it again and initiate a new one after internal review. Dear fange. Please don't top-post and don't send HDMI emails. Looking forward to reviewing v2 of these patches. > > Thanks for your comments. > > Best regards, > fange > > ________________________________ > From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Sent: Monday, October 14, 2024 18:48 > To: fange zhang (QUIC) <quic_fangez@quicinc.com> > Cc: kernel <kernel@quicinc.com>; Li Liu (QUIC) <quic_lliu6@quicinc.com>; Xiangxu Yin (QUIC) <quic_xiangxuy@quicinc.com>; linux-arm-msm@vger.kernel.org <linux-arm-msm@vger.kernel.org> > Subject: Re: [PATCH 0/6] add_display_support_for_QCS615 > > WARNING: This email originated from outside of Qualcomm. Please be wary of any links or attachments, and do not enable macros. > > On Mon, Oct 14, 2024 at 01:36:52PM +0300, Dmitry Baryshkov wrote: > > On Mon, Oct 14, 2024 at 05:47:26PM +0800, fangez via B4 Relay wrote: > > > Signed-off-by: fangez <quic_fangez@quicinc.com> > > > > You didn't copy any of corresponding maintainers or mailing lists, so > > most likely your patches will be ignored. Please use b4 tool for > > preparing and sending patches. > > > > Ok, you are using b4, excuse me. Then it makes me wonder, how and why > you ignored all B4 recommendations and pleads to get required To/Cc > lists. > > > > --- > > > lliu6 (6): > > > arm64: defconfig: Enable SX150X > > > arm64: dts: qcom: qcs615: Add display mdss and dsi configuration > > > drm/msm/dpu: Add QCS615 support > > > dt-bindings: display/msm: Add QCS615 DSI phy > > > dt-bindings: display/msm: Add QCS615 MDSS & DPU > > > dt-bindings: display/msm: dsi-controller-main: Document QCS615 > > > > > > .../bindings/display/msm/dsi-controller-main.yaml | 1 + > > > .../bindings/display/msm/dsi-phy-14nm.yaml | 1 + > > > .../bindings/display/msm/qcom,qcs615-dpu.yaml | 117 +++++++++ > > > .../bindings/display/msm/qcom,qcs615-mdss.yaml | 278 +++++++++++++++++++++ > > > arch/arm64/boot/dts/qcom/qcs615-ride.dts | 101 ++++++++ > > > arch/arm64/boot/dts/qcom/qcs615.dtsi | 195 +++++++++++++++ > > > arch/arm64/configs/defconfig | 1 + > > > .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h | 268 ++++++++++++++++++++ > > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + > > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + > > > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + > > > drivers/gpu/drm/msm/dsi/dsi_cfg.c | 17 ++ > > > drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + > > > drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 + > > > drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + > > > drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 21 ++ > > > drivers/gpu/drm/msm/msm_mdss.c | 7 + > > > 17 files changed, 1014 insertions(+) > > > --- > > > base-commit: 77dca4e0530173cb10896cc113f14e6403f0a31a > > > change-id: 20241014-add_display_support_for_qcs615-b17bc0d4118e > > > > > > Best regards, > > > -- > > > fangez <quic_fangez@quicinc.com> > > > > > > > > > > -- > > With best wishes > > Dmitry > > -- > With best wishes > Dmitry
Signed-off-by: fangez <quic_fangez@quicinc.com> --- lliu6 (6): arm64: defconfig: Enable SX150X arm64: dts: qcom: qcs615: Add display mdss and dsi configuration drm/msm/dpu: Add QCS615 support dt-bindings: display/msm: Add QCS615 DSI phy dt-bindings: display/msm: Add QCS615 MDSS & DPU dt-bindings: display/msm: dsi-controller-main: Document QCS615 .../bindings/display/msm/dsi-controller-main.yaml | 1 + .../bindings/display/msm/dsi-phy-14nm.yaml | 1 + .../bindings/display/msm/qcom,qcs615-dpu.yaml | 117 +++++++++ .../bindings/display/msm/qcom,qcs615-mdss.yaml | 278 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/qcs615-ride.dts | 101 ++++++++ arch/arm64/boot/dts/qcom/qcs615.dtsi | 195 +++++++++++++++ arch/arm64/configs/defconfig | 1 + .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_qcs615.h | 268 ++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + drivers/gpu/drm/msm/dsi/dsi_cfg.c | 17 ++ drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 21 ++ drivers/gpu/drm/msm/msm_mdss.c | 7 + 17 files changed, 1014 insertions(+) --- base-commit: 77dca4e0530173cb10896cc113f14e6403f0a31a change-id: 20241014-add_display_support_for_qcs615-b17bc0d4118e Best regards,