Message ID | 20241017-sa8775p-cpufreq-l3-ddr-scaling-v1-0-074e0fb80b33@quicinc.com |
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Thu, 17 Oct 2024 09:28:44 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49H9ShfD015584 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Oct 2024 09:28:43 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 17 Oct 2024 02:28:38 -0700 From: Jagadeesh Kona <quic_jkona@quicinc.com> Subject: [PATCH 0/3] Add support to scale DDR and L3 on SA8775P Date: Thu, 17 Oct 2024 14:58:29 +0530 Message-ID: <20241017-sa8775p-cpufreq-l3-ddr-scaling-v1-0-074e0fb80b33@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: <linux-arm-msm.vger.kernel.org> List-Subscribe: <mailto:linux-arm-msm+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-arm-msm+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; 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Add support to scale DDR and L3 on SA8775P
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Add support to scale DDR and L3 based on CPU frequencies on Qualcomm SA8775P platform. Also add support for LMH interrupts to indicate if there is any thermal throttle. The changes in this series are dependent on below series changes: https://lore.kernel.org/linux-arm-msm/20240904171209.29120-1-quic_rlaggysh@quicinc.com/#t Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> --- Jagadeesh Kona (2): arm64: dts: qcom: sa8775p: Add support to scale DDR/L3 arm64: dts: qcom: sa8775p: Add LMH interrupts support Shivnandan Kumar (1): arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 215 ++++++++++++++++++++++++++++++++++ 1 file changed, 215 insertions(+) --- base-commit: d1ef2d48e83b32417eb55480c097737364535405 change-id: 20241017-sa8775p-cpufreq-l3-ddr-scaling-a1a9abce98c6 Best regards,