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[00/12] Add support for videocc, camcc, dispcc and gpucc on Qualcomm QCS615 platform

Message ID 20241019-qcs615-mm-clockcontroller-v1-0-9f1ca2048287@quicinc.com
Headers show
Series Add support for videocc, camcc, dispcc and gpucc on Qualcomm QCS615 platform | expand

Message

Taniya Das Oct. 18, 2024, 7:12 p.m. UTC
Add support for multimedia clock controllers on Qualcomm QCS615 platform.
Update the defconfig to enable these clock controllers.

Global clock controller support
https://lore.kernel.org/all/20240920-qcs615-clock-driver-v2-0-2f6de44eb2aa@quicinc.com/

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
Taniya Das (12):
      clk: qcom: Update the support for alpha mode configuration
      clk: qcom: clk-alpha-pll: Add support for dynamic update for slewing PLLs
      dt-bindings: clock: Add Qualcomm QCS615 Camera clock controller
      clk: qcom: camcc-qcs615: Add QCS615 camera clock controller driver
      dt-bindings: clock: qcom: Add QCS615 GCC clocks
      dt-bindings: clock: Add Qualcomm QCS615 Display clock controller
      clk: qcom: dispcc-qcs615: Add QCS615 display clock controller driver
      dt-bindings: clock: Add Qualcomm QCS615 Graphics clock controller
      clk: qcom: gpucc-qcs615: Add QCS615 graphics clock controller driver
      dt-bindings: clock: Add Qualcomm QCS615 Video clock controller
      clk: qcom: videocc-qcs615: Add QCS615 video clock controller driver
      arm64: defconfig: Enable QCS615 clock controllers

 .../bindings/clock/qcom,qcs615-camcc.yaml          |   60 +
 .../bindings/clock/qcom,qcs615-dispcc.yaml         |   73 +
 .../devicetree/bindings/clock/qcom,qcs615-gcc.yaml |   59 +
 .../bindings/clock/qcom,qcs615-gpucc.yaml          |   66 +
 .../bindings/clock/qcom,qcs615-videocc.yaml        |   64 +
 arch/arm64/configs/defconfig                       |    4 +
 drivers/clk/qcom/Kconfig                           |   35 +
 drivers/clk/qcom/Makefile                          |    4 +
 drivers/clk/qcom/camcc-qcs615.c                    | 1588 ++++++++++++++++++++
 drivers/clk/qcom/clk-alpha-pll.c                   |  174 +++
 drivers/clk/qcom/clk-alpha-pll.h                   |    1 +
 drivers/clk/qcom/dispcc-qcs615.c                   |  786 ++++++++++
 drivers/clk/qcom/gpucc-qcs615.c                    |  525 +++++++
 drivers/clk/qcom/videocc-qcs615.c                  |  332 ++++
 include/dt-bindings/clock/qcom,qcs615-camcc.h      |  110 ++
 include/dt-bindings/clock/qcom,qcs615-dispcc.h     |   52 +
 include/dt-bindings/clock/qcom,qcs615-gcc.h        |  211 +++
 include/dt-bindings/clock/qcom,qcs615-gpucc.h      |   39 +
 include/dt-bindings/clock/qcom,qcs615-videocc.h    |   30 +
 19 files changed, 4213 insertions(+)
---
base-commit: 15e7d45e786a62a211dd0098fee7c57f84f8c681
change-id: 20241016-qcs615-mm-clockcontroller-cff9aea7a006

Best regards,

Comments

Krzysztof Kozlowski Oct. 21, 2024, 7:15 a.m. UTC | #1
On Sat, Oct 19, 2024 at 12:42:35AM +0530, Taniya Das wrote:
> Add device tree bindings for global clock controller on QCS615 SoCs.
> 
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> ---

That's 5/12 but rest is missing. Are you sure you used sent it
correctly?

>  .../devicetree/bindings/clock/qcom,qcs615-gcc.yaml |  59 ++++++
>  include/dt-bindings/clock/qcom,qcs615-gcc.h        | 211 +++++++++++++++++++++
>  2 files changed, 270 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,qcs615-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qcs615-gcc.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..fecc694cd71b8aeb3d420ccea5f5ffba04c8ff9c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,qcs615-gcc.yaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,qcs615-gcc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Global Clock & Reset Controller on QCS615
> +
> +maintainers:
> +  - Taniya Das <quic_tdas@quicinc.com>
> +
> +description: |
> +  Qualcomm global clock control module provides the clocks, resets and power
> +  domains on QCS615.
> +
> +  See also:: include/dt-bindings/clock/qcom,qcs615-gcc.h

s/::/:/

> +
> +properties:
> +  compatible:
> +    const: qcom,qcs615-gcc
> +
> +  clocks:
> +    items:
> +      - description: Board XO source
> +      - description: Board active XO source
> +      - description: Sleep clock source
> +
> +  clock-names:
> +    items:
> +      - const: bi_tcxo
> +      - const: bi_tcxo_ao
> +      - const: sleep_clk

That's just "sleep".

Why do you need clock-names in the first place?

Best regards,
Krzysztof
Taniya Das Oct. 21, 2024, 7:36 a.m. UTC | #2
On 10/21/2024 12:45 PM, Krzysztof Kozlowski wrote:
> On Sat, Oct 19, 2024 at 12:42:35AM +0530, Taniya Das wrote:
>> Add device tree bindings for global clock controller on QCS615 SoCs.
>>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> ---
> 
> That's 5/12 but rest is missing. Are you sure you used sent it
> correctly?

Please help review: 
https://patchwork.kernel.org/project/linux-clk/cover/20241019-qcs615-mm-clockcontroller-v1-0-4cfb96d779ae@quicinc.com/ 


> 
>>   .../devicetree/bindings/clock/qcom,qcs615-gcc.yaml |  59 ++++++
>>   include/dt-bindings/clock/qcom,qcs615-gcc.h        | 211 +++++++++++++++++++++
>>   2 files changed, 270 insertions(+)
>>