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Tue, 22 Oct 2024 11:53:00 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 22 Oct 2024 04:52:56 -0700 From: Taniya Das Subject: [PATCH v4 0/4] Add GCC and RPMH clock controller for QCS615 SoC Date: Tue, 22 Oct 2024 17:22:49 +0530 Message-ID: <20241022-qcs615-clock-driver-v4-0-3d716ad0d987@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIABKSF2cC/32NQQ6CMBBFr0JmbU1bC1pW3sOwwOkoE5VKi42Gc HcrLty5fC/5708QKTBFqIsJAiWO7PsMZlUAdm1/JsEuM2ipjbTKigFjpUqBV48X4QInCsJtTXs kV9ldaSAv74FO/Fyqh+bLgYZHjo8/2XEcfXgtz0l97P+TpIQUpUKJaDVtWr3PReQe1+hv0Mzz/ AZIBIqqzQAAAA== X-Change-ID: 20240919-qcs615-clock-driver-d74abed69854 To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Richard Cochran CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , , "Krzysztof Kozlowski" , Dmitry Baryshkov X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: sgcEyUoP0qZtF08GddCMrCrMK6wlbg-r X-Proofpoint-GUID: sgcEyUoP0qZtF08GddCMrCrMK6wlbg-r X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 malwarescore=0 mlxscore=0 suspectscore=0 spamscore=0 impostorscore=0 phishscore=0 mlxlogscore=999 lowpriorityscore=0 clxscore=1011 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410220076 Add support for Global clock controller(GCC) and the RPMH clock controller for the Qualcomm QCS615 SoC. The QCS615 SoC is added as part of the below series. https://lore.kernel.org/all/20240913-add_initial_support_for_qcs615-v2-0-9236223e7dab@quicinc.com/ Signed-off-by: Taniya Das Changes in v4: - Update the comment in the code where gpll0_out_aux2_div and gpll3_out_aux2_div are fixed divider clocks and not the PLL output clocks. [Dmitry] - Link to v3: https://lore.kernel.org/lkml/20241016-qcs615-clock-driver-v3-0-bb5d4135db45@quicinc.com Changes in v3: - Update the gcc_pcie_0_aux_clk_src to use clk_rcg2_shared_ops. [Dmitry] - Remove an extra line [Dmitry] - Link to v2: https://lore.kernel.org/lkml/20240920-qcs615-clock-driver-v2-0-2f6de44eb2aa@quicinc.com --- Changes in v2: - Update the compatible in alphabetical order for RPMHCC bindings and driver. - Remove the extra ":" from the GCC bindings. - Update the GCC Kconfig for some required configs and move the GCC init from module to subsys_initcall(). - Link to v1: https://lore.kernel.org/r/20240919-qcs615-clock-driver-v1-0-51c0cc92e3a2@quicinc.com --- Taniya Das (4): dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for QCS615 clk: qcom: rpmhcc: Add support for QCS615 Clocks dt-bindings: clock: qcom: Add QCS615 GCC clocks clk: qcom: gcc: Add support for QCS615 GCC clocks .../devicetree/bindings/clock/qcom,qcs615-gcc.yaml | 59 + .../devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-rpmh.c | 19 + drivers/clk/qcom/gcc-qcs615.c | 3034 ++++++++++++++++++++ include/dt-bindings/clock/qcom,qcs615-gcc.h | 211 ++ 7 files changed, 3334 insertions(+) --- base-commit: 55bcd2e0d04c1171d382badef1def1fd04ef66c5 change-id: 20240919-qcs615-clock-driver-d74abed69854 Best regards,