Message ID | 20241213-qcs615-gpu-dt-v2-0-47f3b312b178@quicinc.com |
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Devicetree changes for QCS615's GPU
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On 13.12.2024 4:09 PM, Konrad Dybcio wrote: > On 13.12.2024 12:31 PM, Akhil P Oommen wrote: >> From: Jie Zhang <quic_jiezh@quicinc.com> >> >> Add gpu and gmu nodes for qcs615 chipset. >> >> Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com> >> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> >> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> --- > > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Well I forgot I made comments on the non-resend version https://lore.kernel.org/linux-arm-msm/a44027ee-40d3-4552-8f61-bcab77476f68@oss.qualcomm.com/ Konrad
This series adds support for Adreno 612 to QCS615 chipset's devicetree. DRM driver's support was posted earlier and can be found here: https://patchwork.freedesktop.org/patch/626066/ Patch#1 & #2 are for Rob Clark and the other 2 for Bjorn Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> --- Changes in v2: - Completely describe RGMU in devicetree and also add necessary binding documentation (Konrad, feedback on the driver patch) - Remove smmu_vote clk from clock list (Konrad) - Add R-b from Dmitry - Link to v1: https://lore.kernel.org/r/20241126-qcs615-gpu-dt-v1-0-a87782976dad@quicinc.com --- Akhil P Oommen (2): dt-bindings: display/msm: gpu: Document A612 GPU dt-bindings: display/msm/gmu: Document RGMU Jie Zhang (2): arm64: dts: qcom: qcs615: Add gpu and gmu nodes arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU .../devicetree/bindings/display/msm/gmu.yaml | 7 +- .../devicetree/bindings/display/msm/gpu.yaml | 36 +++++++++ arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8 ++ arch/arm64/boot/dts/qcom/qcs615.dtsi | 88 ++++++++++++++++++++++ 4 files changed, 137 insertions(+), 2 deletions(-) --- base-commit: 30eb6f0b08b13fd25ea12a3a6fa0a85915190c1c change-id: 20241125-qcs615-gpu-dt-facbd8ac318f prerequisite-message-id: <20241104-add_initial_support_for_qcs615-v5-4-9dde8d7b80b0@quicinc.com> prerequisite-patch-id: 09782474af7eecf1013425fd34f9d2f082fb3616 prerequisite-patch-id: 04ca722967256efddc402b7bab94136a5174b0b9 prerequisite-patch-id: 82481c82a20345548e2cb292d3098ed51843b809 prerequisite-patch-id: 3bd8edd83297815fcb1b81fcd891d3c14908442f prerequisite-patch-id: fc1cfec4ecd56e669c161c4d2c3797fc0abff0ae prerequisite-message-id: <20241022-qcs615-clock-driver-v4-3-3d716ad0d987@quicinc.com> prerequisite-patch-id: cd9fc0a399ab430e293764d0911a38109664ca91 prerequisite-patch-id: 07f2c7378c7bbd560f26b61785b6814270647f1b prerequisite-patch-id: a57054b890d767b45cca87e71b4a0f6bf6914c2f prerequisite-patch-id: 5a8e9ea15a2c3d60b4dbdf11b4e2695742d6333c prerequisite-message-id: <20240924143958.25-2-quic_rlaggysh@quicinc.com> prerequisite-patch-id: 3c73bafb074ea339d387a6aa39e5362c8775596d prerequisite-patch-id: 0e224a7310d36e9a633d57c4a177ff24c1e8e767 prerequisite-message-id: <20241108-qcs615-mm-clockcontroller-v3-7-7d3b2d235fdf@quicinc.com> prerequisite-patch-id: 748a4e51bbedae9c6ebdbd642b2fd1badf958788 prerequisite-patch-id: 72a894a3b19fdbd431e1cec9397365bc5b27abfe prerequisite-patch-id: da2b7a74f1afd58833c6a9a4544a0e271720641f prerequisite-patch-id: 40b79fe0b9101f5db3bddad23551c1123572aee5 prerequisite-patch-id: cb93e5798f6bfe8cc3044c4ce973e3ae5f20dc6b prerequisite-patch-id: 13b0dbf97ac1865d241791afb4b46a28ca499523 prerequisite-patch-id: 807019bedabd47c04f7ac78e9461d0b5a6e9131b prerequisite-patch-id: 8e2e841401fefbd96d78dd4a7c47514058c83bf2 prerequisite-patch-id: 125bb8cb367109ba22cededf6e78754579e1ed03 prerequisite-patch-id: b3cc42570d5826a4704f7702e7b26af9a0fe57b0 prerequisite-patch-id: df8e2fdd997cbf6c0a107f1871ed9e2caaa97582 prerequisite-message-id: <20241108-qcs615-mm-dt-nodes-v1-1-b2669cac0624@quicinc.com> prerequisite-patch-id: bcb1328b70868bb9c87c0e4c48e5c9d38853bc60 prerequisite-patch-id: 8844a4661902eb44406639a3b7344416a0c88ed9 prerequisite-message-id: <20241122074922.28153-1-quic_qqzhou@quicinc.com> prerequisite-patch-id: 50223f2370a7ae8053b164fa5219a1690d7e4567 prerequisite-patch-id: c71c7897d6f250b381f7a9ac66ec58f4a10d49d6 Best regards,