From patchwork Fri Feb 7 07:39:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 863370 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B80A1A00FE; Fri, 7 Feb 2025 07:40:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738914012; cv=none; b=QvobzIuqvFPn1Yt1mMo2eFZM39rRChp0aDzWvPBOo61Wo8TR2ZpIumbmiaSrz3d8nvvPlDm3bYnRu5DqFDNgWI5Fn7BZtO43Q0ih3W0qyZTYQGlt9wh97LQjOUuo0BfeGr2aW9OGRjmTEsVrhznjqBPeIbtLtojskgoimk+HfoE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738914012; c=relaxed/simple; bh=unBdIGofYYswrMGG9V/Det7ZKVOKpYUiXdx7DzCCKZ0=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=AFGVfShP1m61svla4ry1vhtDSvCZI/mjWpczmFU3hbVRY9gc4OAS1hYm1fBRVKnQAUtUX/Vg9pq3LIK/Jomtg9W7Fhhgm1zu778FZCpjK7AiqvogdR+M1RxekGfuoXg1vPZuCdnJUFJseD2jM0n/I5bjpLzgnBnGX9tMO/iExFA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=moR+GT3T; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="moR+GT3T" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 51770ik8030084; Fri, 7 Feb 2025 07:39:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=qcppdkim1; bh=oyzRANn5dmtjvGE1jNRWe6 EuSnAsWWPUVRxFwxxtv6A=; b=moR+GT3TKX1+thVsIsCC4fwrFsUTOdqAJKrS87 bxrMzNbLmQ61xbL94GkNmWxlAlGvRTDelCNS6232C6BflVlj905MOJxe6vmgMk5J uLiDcfYhtYR3Y+/OrG/YGR/Hk6O+BOGXuAsHnlgrZfAKmUbAqAfaby/qoYp3Wc19 L5LYskXcalMGmNkssDhEppiF+e4whzzgFHye5flgGCEAHyvLl2LLv8WrvONOBUOt Doxhh9Wwgg7aFRwPWUWzkqzILz1M+EmQCTBdK+D1SfT5tqGGXOE5baG+1q1Vkpeq +wTGV3wApY9tdXeu7wCxamx/srb09ailNZjO2zoooQ4uCFcQ== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44nddjg2x6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 07 Feb 2025 07:39:46 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5177djsA000543 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 7 Feb 2025 07:39:45 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 6 Feb 2025 23:39:36 -0800 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH v9 0/6] Add NSS clock controller support for IPQ9574 Date: Fri, 7 Feb 2025 13:09:20 +0530 Message-ID: <20250207073926.2735129-1-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: uDi8ZUKtWb1JAjxjPD8u8gRmEOPsuJoI X-Proofpoint-GUID: uDi8ZUKtWb1JAjxjPD8u8gRmEOPsuJoI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-07_03,2025-02-07_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 impostorscore=0 adultscore=0 bulkscore=0 phishscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=737 priorityscore=1501 clxscore=1011 suspectscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502070057 Add bindings, driver and devicetree node for networking sub system clock controller on IPQ9574. Also add support for gpll0_out_aux clock which serves as the parent for some nss clocks. Changes in V9: - Dropped patch #1 because it's merged. - Detailed change logs are added to the respective patches. - Dependency series has been merged. V8 can be found at: https://lore.kernel.org/linux-arm-msm/20241025035520.1841792-1-quic_mmanikan@quicinc.com/ V7 can be found at: https://lore.kernel.org/linux-arm-msm/20241009074125.794997-1-quic_mmanikan@quicinc.com/ V6 can be found at: https://lore.kernel.org/linux-arm-msm/20241004080332.853503-1-quic_mmanikan@quicinc.com/ V5 can be found at: https://lore.kernel.org/linux-arm-msm/20240626143302.810632-1-quic_devipriy@quicinc.com/ V4 can be found at: https://lore.kernel.org/linux-arm-msm/20240625070536.3043630-1-quic_devipriy@quicinc.com/ V3 can be found at: https://lore.kernel.org/linux-arm-msm/20240129051104.1855487-1-quic_devipriy@quicinc.com/ V2 can be found at: https://lore.kernel.org/linux-arm-msm/20230825091234.32713-1-quic_devipriy@quicinc.com/ Devi Priya (6): dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux clock dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions clk: qcom: Add NSS clock Controller driver for IPQ9574 arm64: dts: qcom: ipq9574: Add nsscc node arm64: defconfig: Build NSS Clock Controller driver for IPQ9574 .../bindings/clock/qcom,ipq9574-nsscc.yaml | 73 + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 19 + arch/arm64/configs/defconfig | 1 + drivers/clk/qcom/Kconfig | 7 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-ipq9574.c | 15 + drivers/clk/qcom/nsscc-ipq9574.c | 3080 +++++++++++++++++ include/dt-bindings/clock/qcom,ipq9574-gcc.h | 1 + .../dt-bindings/clock/qcom,ipq9574-nsscc.h | 152 + .../dt-bindings/reset/qcom,ipq9574-nsscc.h | 134 + 10 files changed, 3483 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c create mode 100644 include/dt-bindings/clock/qcom,ipq9574-nsscc.h create mode 100644 include/dt-bindings/reset/qcom,ipq9574-nsscc.h base-commit: ed88b8b82c53d73ca0428e31c2eba3984e32140d