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Thu, 6 Mar 2025 08:55:52 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 6 Mar 2025 00:55:47 -0800 From: Jagadeesh Kona Subject: [PATCH v2 0/8] clk: qcom: Add support to attach multiple power domains in cc probe Date: Thu, 6 Mar 2025 14:25:32 +0530 Message-ID: <20250306-videocc-pll-multi-pd-voting-v2-0-0cd00612bc0e@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAARjyWcC/43NQQ6CMBCF4auYWTumbRTBlfcwLHA6wCTQYguNh nB3Kydw+b3F/1aIHIQj3A4rBE4SxbsMczwA9Y3rGMVmg1HmoowuMYllT4TTMOC4DLPgZDH5WVy HttBnS1xpxVfIhSlwK++9/qize4mzD5/9LOnf+l83aVRILRemrLgx1fP+WoTE0Yn8CPW2bV+2d Ea3yAAAAA== X-Change-ID: 20250218-videocc-pll-multi-pd-voting-d614dce910e7 To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Jagadeesh Kona , Bryan O'Donoghue , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: zjQy09dJM6xidmzX-_NLhR44McM8i8rZ X-Authority-Analysis: v=2.4 cv=cOIaskeN c=1 sm=1 tr=0 ts=67c96319 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=xpdHRz03M5ydJ-6NNugA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: zjQy09dJM6xidmzX-_NLhR44McM8i8rZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-06_04,2025-03-06_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 suspectscore=0 adultscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 mlxscore=0 impostorscore=0 mlxlogscore=991 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503060067 In some of the recent chipsets, PLLs require more than one power domain to be kept ON to configure the PLL. But the current code doesn't enable all the required power domains while configuring the PLLs, this leads to functional issues due to suboptimal settings of PLLs. To address this, add support for handling runtime power management, configuring plls and enabling critical clocks from qcom_cc_really_probe. The clock controller can specify PLLs, critical clocks, and runtime PM requirements in the descriptor data. The code in qcom_cc_really_probe() ensures all necessary power domains are enabled before configuring PLLs or critical clocks. This series updates SM8450 & SM8550 videocc drivers to handle rpm, configure PLLs and enable critical clocks from within qcom_cc_really_probe() using above support, so video PLLs are configured properly. This series fixes the below warning reported in SM8550 venus testing due to video_cc_pll0 not properly getting configured during videocc probe [ 46.535132] Lucid PLL latch failed. Output may be unstable! The patch adding support to configure the PLLs from common code is picked from below series and updated it. https://lore.kernel.org/all/20250113-support-pll-reconfigure-v1-0-1fae6bc1062d@quicinc.com/ Signed-off-by: Jagadeesh Kona --- Changes in v2: - Added support to handle rpm, PLL configuration and enable critical clocks from qcom_cc_really_probe() in common code as per v1 commments from Bryan, Konrad and Dmitry - Added patches to configure PLLs from common code - Updated the SM8450, SM8550 videocc patches to use the newly added support to handle rpm, configure PLLs from common code - Split the DT change for each target separately as per Dmitry comments - Added R-By and A-By tags received on v1 - Link to v1: https://lore.kernel.org/r/20250218-videocc-pll-multi-pd-voting-v1-0-cfe6289ea29b@quicinc.com --- Jagadeesh Kona (7): dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain clk: qcom: common: Manage rpm, configure PLLs & AON clks in really probe clk: qcom: videocc-sm8450: Move PLL & clk configuration to really probe clk: qcom: videocc-sm8550: Move PLL & clk configuration to really probe arm64: dts: qcom: Add MXC power domain to videocc node on SM8450 arm64: dts: qcom: Add MXC power domain to videocc node on SM8550 arm64: dts: qcom: Add MXC power domain to videocc node on SM8650 Taniya Das (1): clk: qcom: common: Add support to configure PLL .../bindings/clock/qcom,sm8450-videocc.yaml | 9 +- arch/arm64/boot/dts/qcom/sm8450.dtsi | 3 +- arch/arm64/boot/dts/qcom/sm8550.dtsi | 3 +- arch/arm64/boot/dts/qcom/sm8650.dtsi | 3 +- drivers/clk/qcom/clk-alpha-pll.h | 2 + drivers/clk/qcom/common.c | 100 +++++++++++++++++++-- drivers/clk/qcom/common.h | 17 ++++ drivers/clk/qcom/videocc-sm8450.c | 49 +++++----- drivers/clk/qcom/videocc-sm8550.c | 50 +++++------ 9 files changed, 167 insertions(+), 69 deletions(-) --- base-commit: e5d3fd687aac5eceb1721fa92b9f49afcf4c3717 change-id: 20250218-videocc-pll-multi-pd-voting-d614dce910e7 Best regards,