| Message ID | 20250519-dpu-drop-features-v4-0-6c5e88e31383@oss.qualcomm.com |
|---|---|
| Headers | show |
| Series | drm/msm/dpu: rework HW block feature handling | expand |
On 19/05/2025 18:04, Dmitry Baryshkov wrote: > From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > Continue migration to the MDSS-revision based checks and replace > DPU_MDP_PERIPH_0_REMOVED feature bit with the core_major_ver >= 8 check. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> > --- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 1 - > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 1 - > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 1 - > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 1 - > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 1 - > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 1 - > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 1 - > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 2 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +- > 10 files changed, 2 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h > index 37c88b393c12d8a04395b6e5dffb67211d2db9cd..ae66c338250664f9306a7d431cfa18ca07a916a5 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h > @@ -21,7 +21,6 @@ static const struct dpu_caps sm8650_dpu_caps = { > static const struct dpu_mdp_cfg sm8650_mdp = { > .name = "top_0", > .base = 0, .len = 0x494, > - .features = BIT(DPU_MDP_PERIPH_0_REMOVED), > .clk_ctrls = { > [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, > }, > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h > index 785ca2b2e60f073b0a2db0c0c4ed3b2722de033c..85778071bc1347008dbe4522aeb9ca4fd21aa097 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h > @@ -21,7 +21,6 @@ static const struct dpu_caps sc8280xp_dpu_caps = { > static const struct dpu_mdp_cfg sc8280xp_mdp = { > .name = "top_0", > .base = 0x0, .len = 0x494, > - .features = BIT(DPU_MDP_PERIPH_0_REMOVED), > .clk_ctrls = { > [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, > [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h > index 1401a84e0da5754fd2a3661d1421bb9b998271ca..f9676f804f9132296467bc751e11036696afa942 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h > @@ -21,7 +21,6 @@ static const struct dpu_caps sm8450_dpu_caps = { > static const struct dpu_mdp_cfg sm8450_mdp = { > .name = "top_0", > .base = 0x0, .len = 0x494, > - .features = BIT(DPU_MDP_PERIPH_0_REMOVED), > .clk_ctrls = { > [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, > [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h > index fbbdce36f0ad99d0b1d32d90627ff5b7f3fc2fc9..7462cfc4cf8de4a10326c83d3341dbee76e437e8 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h > @@ -20,7 +20,6 @@ static const struct dpu_caps sa8775p_dpu_caps = { > static const struct dpu_mdp_cfg sa8775p_mdp = { > .name = "top_0", > .base = 0x0, .len = 0x494, > - .features = BIT(DPU_MDP_PERIPH_0_REMOVED), > .clk_ctrls = { > [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, > [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h > index cc4413432cfdc636e38a56011d39f18d7e94c23a..695ae7581a88b36fa1f28aa3cd0c9166090e940c 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h > @@ -21,7 +21,6 @@ static const struct dpu_caps sm8550_dpu_caps = { > static const struct dpu_mdp_cfg sm8550_mdp = { > .name = "top_0", > .base = 0, .len = 0x494, > - .features = BIT(DPU_MDP_PERIPH_0_REMOVED), > .clk_ctrls = { > [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, > }, > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h > index 32f88533154584dc98a515b1ddef27ab2005fecd..9a25113df5aec527baa514aaa61f2b47c2443d27 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h > @@ -21,7 +21,6 @@ static const struct dpu_caps sar2130p_dpu_caps = { > static const struct dpu_mdp_cfg sar2130p_mdp = { > .name = "top_0", > .base = 0, .len = 0x494, > - .features = BIT(DPU_MDP_PERIPH_0_REMOVED), > .clk_ctrls = { > [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, > }, > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h > index e053324d76a2e5020e6a7477ddadc9f7d94fe57e..54815c613f087454aa7b4befc84462265d8dfc23 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h > @@ -20,7 +20,6 @@ static const struct dpu_caps x1e80100_dpu_caps = { > static const struct dpu_mdp_cfg x1e80100_mdp = { > .name = "top_0", > .base = 0, .len = 0x494, > - .features = BIT(DPU_MDP_PERIPH_0_REMOVED), > .clk_ctrls = { > [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, > }, > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 92dfbb5e7f916bf32afeffdb6b843f1da3f3fd44..d3a7f46488a21e81a24a9af5071a9a7f5f48cdac 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -32,8 +32,6 @@ > * MDP TOP BLOCK features > * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be done per pipe > * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats > - * @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0 block results > - * in a failure > * @DPU_MDP_MAX Maximum value > > */ > @@ -41,7 +39,6 @@ enum { > DPU_MDP_PANIC_PER_PIPE = 0x1, > DPU_MDP_10BIT_SUPPORT, > DPU_MDP_AUDIO_SELECT, > - DPU_MDP_PERIPH_0_REMOVED, > DPU_MDP_MAX > }; > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c > index cebe7ce7b258fc178a687770906f7c4c20aa0d4c..c49a67da86b0d46d12c32466981be7f00519974c 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c > @@ -272,7 +272,7 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops, > > if (mdss_rev->core_major_ver < 5) > ops->setup_vsync_source = dpu_hw_setup_vsync_sel; > - else if (!(cap & BIT(DPU_MDP_PERIPH_0_REMOVED))) > + else if (mdss_rev->core_major_ver < 8) > ops->setup_vsync_source = dpu_hw_setup_wd_timer; > > ops->get_safe_status = dpu_hw_get_safe_status; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > index 1fd82b6747e9058ce11dc2620729921492d5ebdd..80ffd46cbfe69fc90afcdc1a144fc5de7bb6af42 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > @@ -1022,7 +1022,7 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k > dpu_kms->mmio + cat->wb[i].base, "%s", > cat->wb[i].name); > > - if (cat->mdp[0].features & BIT(DPU_MDP_PERIPH_0_REMOVED)) { > + if (dpu_kms->catalog->mdss_ver->core_major_ver >= 8) { > msm_disp_snapshot_add_block(disp_state, MDP_PERIPH_TOP0, > dpu_kms->mmio + cat->mdp[0].base, "top"); > msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - MDP_PERIPH_TOP0_END, > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
On 19/05/2025 18:04, Dmitry Baryshkov wrote: > From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > Continue migration to the MDSS-revision based checks and replace > DPU_PINGPONG_DITHER feature bit with the core_major_ver >= 3 check. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> > --- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 10 ---------- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 4 ---- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 4 ---- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 2 -- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 4 ---- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 6 ------ > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 ------ > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 4 ---- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 3 --- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 2 -- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 6 ------ > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 2 -- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 - > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 2 -- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 - > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 - > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 6 ------ > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 4 ---- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 6 ------ > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 8 -------- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 8 -------- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 8 -------- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 8 -------- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 8 -------- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 ------ > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 2 +- > 27 files changed, 1 insertion(+), 123 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h > index 88582fc257dea342f05b93dae6afe986eb7f32d0..37c88b393c12d8a04395b6e5dffb67211d2db9cd 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h > @@ -203,67 +203,57 @@ static const struct dpu_pingpong_cfg sm8650_pp[] = { > { > .name = "pingpong_0", .id = PINGPONG_0, > .base = 0x69000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > }, { > .name = "pingpong_1", .id = PINGPONG_1, > .base = 0x6a000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > }, { > .name = "pingpong_2", .id = PINGPONG_2, > .base = 0x6b000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_1, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), > }, { > .name = "pingpong_3", .id = PINGPONG_3, > .base = 0x6c000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_1, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), > }, { > .name = "pingpong_4", .id = PINGPONG_4, > .base = 0x6d000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_2, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), > }, { > .name = "pingpong_5", .id = PINGPONG_5, > .base = 0x6e000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_2, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), > }, { > .name = "pingpong_cwb_0", .id = PINGPONG_CWB_0, > .base = 0x66000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_3, > }, { > .name = "pingpong_cwb_1", .id = PINGPONG_CWB_1, > .base = 0x66400, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_3, > }, { > .name = "pingpong_cwb_2", .id = PINGPONG_CWB_2, > .base = 0x7e000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_4, > }, { > .name = "pingpong_cwb_3", .id = PINGPONG_CWB_3, > .base = 0x7e400, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_4, > }, > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h > index 91285519c540025abce5c51f2f28442ed9d479b0..f2ec30837f9ccbff1041f0465d0123382a00355a 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h > @@ -170,28 +170,24 @@ static const struct dpu_pingpong_cfg msm8998_pp[] = { > { > .name = "pingpong_0", .id = PINGPONG_0, > .base = 0x70000, .len = 0xd4, > - .features = PINGPONG_SDM845_MASK, > .sblk = &sdm845_pp_sblk, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), > }, { > .name = "pingpong_1", .id = PINGPONG_1, > .base = 0x70800, .len = 0xd4, > - .features = PINGPONG_SDM845_MASK, > .sblk = &sdm845_pp_sblk, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), > }, { > .name = "pingpong_2", .id = PINGPONG_2, > .base = 0x71000, .len = 0xd4, > - .features = PINGPONG_SDM845_MASK, > .sblk = &sdm845_pp_sblk, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), > .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14), > }, { > .name = "pingpong_3", .id = PINGPONG_3, > .base = 0x71800, .len = 0xd4, > - .features = PINGPONG_SDM845_MASK, > .sblk = &sdm845_pp_sblk, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), > .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15), > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h > index 50e0e3aec23c02acc1ce2d2a8a5658d6d49a62ac..26f39acd82e07c71cbeaaa72c14d9b7e14d2dcc3 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h > @@ -141,28 +141,24 @@ static const struct dpu_pingpong_cfg sdm660_pp[] = { > { > .name = "pingpong_0", .id = PINGPONG_0, > .base = 0x70000, .len = 0xd4, > - .features = PINGPONG_SDM845_MASK, > .sblk = &sdm845_pp_sblk, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), > }, { > .name = "pingpong_1", .id = PINGPONG_1, > .base = 0x70800, .len = 0xd4, > - .features = PINGPONG_SDM845_MASK, > .sblk = &sdm845_pp_sblk, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), > }, { > .name = "pingpong_2", .id = PINGPONG_2, > .base = 0x71000, .len = 0xd4, > - .features = PINGPONG_SDM845_MASK, > .sblk = &sdm845_pp_sblk, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), > .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14), > }, { > .name = "pingpong_3", .id = PINGPONG_3, > .base = 0x71800, .len = 0xd4, > - .features = PINGPONG_SDM845_MASK, > .sblk = &sdm845_pp_sblk, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), > .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15), > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h > index 1c299491e61f0465a164be74b7a754435f347cb6..657f733c9ffff73f9eb5051ba55ed2e4e7bb496d 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h > @@ -115,14 +115,12 @@ static const struct dpu_pingpong_cfg sdm630_pp[] = { > { > .name = "pingpong_0", .id = PINGPONG_0, > .base = 0x70000, .len = 0xd4, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sdm845_pp_sblk, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), > }, { > .name = "pingpong_2", .id = PINGPONG_2, > .base = 0x71000, .len = 0xd4, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sdm845_pp_sblk, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), > .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14), > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h > index 50e40405a5271ea6b12caa7a931ff7fe3f2478a8..15da5ded19267711e6df8605d576539475fe634c 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h > @@ -190,28 +190,24 @@ static const struct dpu_pingpong_cfg sdm845_pp[] = { > { > .name = "pingpong_0", .id = PINGPONG_0, > .base = 0x70000, .len = 0xd4, > - .features = PINGPONG_SDM845_MASK, > .sblk = &sdm845_pp_sblk, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), > }, { > .name = "pingpong_1", .id = PINGPONG_1, > .base = 0x70800, .len = 0xd4, > - .features = PINGPONG_SDM845_MASK, > .sblk = &sdm845_pp_sblk, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), > }, { > .name = "pingpong_2", .id = PINGPONG_2, > .base = 0x71000, .len = 0xd4, > - .features = PINGPONG_SDM845_MASK, > .sblk = &sdm845_pp_sblk, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), > .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14), > }, { > .name = "pingpong_3", .id = PINGPONG_3, > .base = 0x71800, .len = 0xd4, > - .features = PINGPONG_SDM845_MASK, > .sblk = &sdm845_pp_sblk, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), > .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15), > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h > index bcab869aafbe1e23e0267bbad377fc10d8c6256d..e07c2cc4188bb12e2253068ca8666ce9364c69c1 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h > @@ -207,42 +207,36 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = { > { > .name = "pingpong_0", .id = PINGPONG_0, > .base = 0x70000, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = MERGE_3D_0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > }, { > .name = "pingpong_1", .id = PINGPONG_1, > .base = 0x70800, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = MERGE_3D_0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > }, { > .name = "pingpong_2", .id = PINGPONG_2, > .base = 0x71000, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = MERGE_3D_1, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), > }, { > .name = "pingpong_3", .id = PINGPONG_3, > .base = 0x71800, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = MERGE_3D_1, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), > }, { > .name = "pingpong_4", .id = PINGPONG_4, > .base = 0x72000, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = MERGE_3D_2, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), > }, { > .name = "pingpong_5", .id = PINGPONG_5, > .base = 0x72800, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = MERGE_3D_2, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h > index 4b61bc7eb79f00a184c95b2319b737fcee6c4cbb..b350dba28caed77e542d6a41ceac191a93e165a7 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h > @@ -207,42 +207,36 @@ static const struct dpu_pingpong_cfg sc8180x_pp[] = { > { > .name = "pingpong_0", .id = PINGPONG_0, > .base = 0x70000, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = MERGE_3D_0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > }, { > .name = "pingpong_1", .id = PINGPONG_1, > .base = 0x70800, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = MERGE_3D_0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > }, { > .name = "pingpong_2", .id = PINGPONG_2, > .base = 0x71000, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = MERGE_3D_1, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), > }, { > .name = "pingpong_3", .id = PINGPONG_3, > .base = 0x71800, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = MERGE_3D_1, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), > }, { > .name = "pingpong_4", .id = PINGPONG_4, > .base = 0x72000, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = MERGE_3D_2, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), > }, { > .name = "pingpong_5", .id = PINGPONG_5, > .base = 0x72800, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = MERGE_3D_2, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h > index 2e7ae68f7e922e9b71d79627806042f645cb4ad2..27c71a8a1f31921e5e1f4b6b15e0efc25fb63537 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h > @@ -156,28 +156,24 @@ static const struct dpu_pingpong_cfg sm7150_pp[] = { > { > .name = "pingpong_0", .id = PINGPONG_0, > .base = 0x70000, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = MERGE_3D_0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > }, { > .name = "pingpong_1", .id = PINGPONG_1, > .base = 0x70800, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = MERGE_3D_0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > }, { > .name = "pingpong_2", .id = PINGPONG_2, > .base = 0x71000, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = MERGE_3D_1, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), > }, { > .name = "pingpong_3", .id = PINGPONG_3, > .base = 0x71800, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = MERGE_3D_1, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h > index a99c99ca37703cc3a7d4403d3f026f234b693319..e2306d314ef8f8b59078a8ca8c529f2e56385c98 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h > @@ -138,19 +138,16 @@ static const struct dpu_pingpong_cfg sm6150_pp[] = { > { > .name = "pingpong_0", .id = PINGPONG_0, > .base = 0x70000, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > }, { > .name = "pingpong_1", .id = PINGPONG_1, > .base = 0x70800, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > }, { > .name = "pingpong_2", .id = PINGPONG_2, > .base = 0x71000, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), > }, > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h > index 72f1328deda87ccc0b97f3f03d5840a77426b2b7..62136811a530a6072accbd1ab3e02e7e24220ccb 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h > @@ -119,14 +119,12 @@ static const struct dpu_pingpong_cfg sm6125_pp[] = { > { > .name = "pingpong_0", .id = PINGPONG_0, > .base = 0x70000, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .merge_3d = 0, > .sblk = &sdm845_pp_sblk, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > }, { > .name = "pingpong_1", .id = PINGPONG_1, > .base = 0x70800, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .merge_3d = 0, > .sblk = &sdm845_pp_sblk, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h > index aee4adb3b73d2efb074abc58dff7d213a73207d9..34f11fb084c02cf994c272196299bb9f7bced4f1 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h > @@ -205,42 +205,36 @@ static const struct dpu_pingpong_cfg sm8250_pp[] = { > { > .name = "pingpong_0", .id = PINGPONG_0, > .base = 0x70000, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = MERGE_3D_0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > }, { > .name = "pingpong_1", .id = PINGPONG_1, > .base = 0x70800, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = MERGE_3D_0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > }, { > .name = "pingpong_2", .id = PINGPONG_2, > .base = 0x71000, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = MERGE_3D_1, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), > }, { > .name = "pingpong_3", .id = PINGPONG_3, > .base = 0x71800, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = MERGE_3D_1, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), > }, { > .name = "pingpong_4", .id = PINGPONG_4, > .base = 0x72000, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = MERGE_3D_2, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), > }, { > .name = "pingpong_5", .id = PINGPONG_5, > .base = 0x72800, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = MERGE_3D_2, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h > index 05c0f81b263c4a9aab8adbfa487f6cd20ce94079..135b4f8171360493e58a1945105f8722d513d720 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h > @@ -111,14 +111,12 @@ static const struct dpu_pingpong_cfg sc7180_pp[] = { > { > .name = "pingpong_0", .id = PINGPONG_0, > .base = 0x70000, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = 0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > }, { > .name = "pingpong_1", .id = PINGPONG_1, > .base = 0x70800, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = 0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h > index b729a01e8ff8443721bf993726ae9ebe21e89440..1189a5ecb3b7b50430eb275280c2309ee9d90b63 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h > @@ -76,7 +76,6 @@ static const struct dpu_pingpong_cfg sm6115_pp[] = { > { > .name = "pingpong_0", .id = PINGPONG_0, > .base = 0x70000, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = 0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h > index 25f56c55f373ef5e57082448bc1a1d1d17968b06..13ff6bdcc517fd566e7701f7a7cefe5ff19c5421 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h > @@ -119,14 +119,12 @@ static struct dpu_pingpong_cfg sm6350_pp[] = { > { > .name = "pingpong_0", .id = PINGPONG_0, > .base = 0x70000, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = 0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > }, { > .name = "pingpong_1", .id = PINGPONG_1, > .base = 0x70800, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = 0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h > index 20b12a68fb9dfe0291486ca827c6ca25a1711014..d4c2d2da91aac0bce46c4d65079f01484a769ae3 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h > @@ -76,7 +76,6 @@ static const struct dpu_pingpong_cfg qcm2290_pp[] = { > { > .name = "pingpong_0", .id = PINGPONG_0, > .base = 0x70000, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = 0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h > index 6935ff7da3162dd7b86f3786b0f604d113e51649..9135853a0225fa60acb80d17f627153d25c612e6 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h > @@ -78,7 +78,6 @@ static const struct dpu_pingpong_cfg sm6375_pp[] = { > { > .name = "pingpong_0", .id = PINGPONG_0, > .base = 0x70000, .len = 0xd4, > - .features = PINGPONG_SM8150_MASK, > .sblk = &sdm845_pp_sblk, > .merge_3d = 0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h > index b6b1a4383efa72fc0bc8a6feac1c3adb7773ba42..6503f11f65c11806c5b9558a0f9fd05b228340be 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h > @@ -205,42 +205,36 @@ static const struct dpu_pingpong_cfg sm8350_pp[] = { > { > .name = "pingpong_0", .id = PINGPONG_0, > .base = 0x69000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > }, { > .name = "pingpong_1", .id = PINGPONG_1, > .base = 0x6a000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > }, { > .name = "pingpong_2", .id = PINGPONG_2, > .base = 0x6b000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_1, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), > }, { > .name = "pingpong_3", .id = PINGPONG_3, > .base = 0x6c000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_1, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), > }, { > .name = "pingpong_4", .id = PINGPONG_4, > .base = 0x6d000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_2, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), > }, { > .name = "pingpong_5", .id = PINGPONG_5, > .base = 0x6e000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_2, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h > index d1dd895acbf666ceab39f9c38ae11bda100b5953..202de6f9b0c65c6f2caa9e9d5232f5b92d8bdf01 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h > @@ -121,28 +121,24 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = { > { > .name = "pingpong_0", .id = PINGPONG_0, > .base = 0x69000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = 0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > }, { > .name = "pingpong_1", .id = PINGPONG_1, > .base = 0x6a000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = 0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > }, { > .name = "pingpong_2", .id = PINGPONG_2, > .base = 0x6b000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = 0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), > }, { > .name = "pingpong_3", .id = PINGPONG_3, > .base = 0x6c000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = 0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h > index 481d36b80c4eddda53d2f9963392d9499f966792..785ca2b2e60f073b0a2db0c0c4ed3b2722de033c 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h > @@ -205,42 +205,36 @@ static const struct dpu_pingpong_cfg sc8280xp_pp[] = { > { > .name = "pingpong_0", .id = PINGPONG_0, > .base = 0x69000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > }, { > .name = "pingpong_1", .id = PINGPONG_1, > .base = 0x6a000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > }, { > .name = "pingpong_2", .id = PINGPONG_2, > .base = 0x6b000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_1, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), > }, { > .name = "pingpong_3", .id = PINGPONG_3, > .base = 0x6c000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_1, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), > }, { > .name = "pingpong_4", .id = PINGPONG_4, > .base = 0x6d000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_2, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), > }, { > .name = "pingpong_5", .id = PINGPONG_5, > .base = 0x6e000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_2, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h > index 32649f25fdcbc1fe45d7028352dfd4c0daa11d84..1401a84e0da5754fd2a3661d1421bb9b998271ca 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h > @@ -206,55 +206,47 @@ static const struct dpu_pingpong_cfg sm8450_pp[] = { > { > .name = "pingpong_0", .id = PINGPONG_0, > .base = 0x69000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > }, { > .name = "pingpong_1", .id = PINGPONG_1, > .base = 0x6a000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > }, { > .name = "pingpong_2", .id = PINGPONG_2, > .base = 0x6b000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_1, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), > }, { > .name = "pingpong_3", .id = PINGPONG_3, > .base = 0x6c000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_1, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), > }, { > .name = "pingpong_4", .id = PINGPONG_4, > .base = 0x6d000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_2, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), > }, { > .name = "pingpong_5", .id = PINGPONG_5, > .base = 0x6e000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_2, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), > }, { > .name = "pingpong_cwb_0", .id = PINGPONG_CWB_0, > .base = 0x65800, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_3, > }, { > .name = "pingpong_cwb_1", .id = PINGPONG_CWB_1, > .base = 0x65c00, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_3, > }, > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h > index 4679b7e47d50e21d5b6df69fd0479b804ac69979..fbbdce36f0ad99d0b1d32d90627ff5b7f3fc2fc9 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h > @@ -205,55 +205,47 @@ static const struct dpu_pingpong_cfg sa8775p_pp[] = { > { > .name = "pingpong_0", .id = PINGPONG_0, > .base = 0x69000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > }, { > .name = "pingpong_1", .id = PINGPONG_1, > .base = 0x6a000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > }, { > .name = "pingpong_2", .id = PINGPONG_2, > .base = 0x6b000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_1, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), > }, { > .name = "pingpong_3", .id = PINGPONG_3, > .base = 0x6c000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_1, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), > }, { > .name = "pingpong_4", .id = PINGPONG_4, > .base = 0x6d000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_2, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), > }, { > .name = "pingpong_5", .id = PINGPONG_5, > .base = 0x6e000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_2, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), > }, { > .name = "pingpong_6", .id = PINGPONG_CWB_0, > .base = 0x65800, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_3, > }, { > .name = "pingpong_7", .id = PINGPONG_CWB_1, > .base = 0x65c00, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_3, > }, > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h > index def7c161d787d9cecd219b4db0482158d3e5bc12..cc4413432cfdc636e38a56011d39f18d7e94c23a 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h > @@ -202,55 +202,47 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = { > { > .name = "pingpong_0", .id = PINGPONG_0, > .base = 0x69000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > }, { > .name = "pingpong_1", .id = PINGPONG_1, > .base = 0x6a000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > }, { > .name = "pingpong_2", .id = PINGPONG_2, > .base = 0x6b000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_1, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), > }, { > .name = "pingpong_3", .id = PINGPONG_3, > .base = 0x6c000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_1, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), > }, { > .name = "pingpong_4", .id = PINGPONG_4, > .base = 0x6d000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_2, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), > }, { > .name = "pingpong_5", .id = PINGPONG_5, > .base = 0x6e000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_2, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), > }, { > .name = "pingpong_cwb_0", .id = PINGPONG_CWB_0, > .base = 0x66000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_3, > }, { > .name = "pingpong_cwb_1", .id = PINGPONG_CWB_1, > .base = 0x66400, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_3, > }, > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h > index 979a674517d8b270309a4ce92534face0f2ba855..32f88533154584dc98a515b1ddef27ab2005fecd 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h > @@ -202,55 +202,47 @@ static const struct dpu_pingpong_cfg sar2130p_pp[] = { > { > .name = "pingpong_0", .id = PINGPONG_0, > .base = 0x69000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > }, { > .name = "pingpong_1", .id = PINGPONG_1, > .base = 0x6a000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > }, { > .name = "pingpong_2", .id = PINGPONG_2, > .base = 0x6b000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_1, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), > }, { > .name = "pingpong_3", .id = PINGPONG_3, > .base = 0x6c000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_1, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), > }, { > .name = "pingpong_4", .id = PINGPONG_4, > .base = 0x6d000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_2, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), > }, { > .name = "pingpong_5", .id = PINGPONG_5, > .base = 0x6e000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_2, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), > }, { > .name = "pingpong_cwb_0", .id = PINGPONG_CWB_0, > .base = 0x66000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_3, > }, { > .name = "pingpong_cwb_1", .id = PINGPONG_CWB_1, > .base = 0x66400, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_3, > }, > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h > index ffee0740ddb5c13dbbd2ca0d70855cba27f73ca6..e053324d76a2e5020e6a7477ddadc9f7d94fe57e 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h > @@ -202,55 +202,47 @@ static const struct dpu_pingpong_cfg x1e80100_pp[] = { > { > .name = "pingpong_0", .id = PINGPONG_0, > .base = 0x69000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > }, { > .name = "pingpong_1", .id = PINGPONG_1, > .base = 0x6a000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_0, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > }, { > .name = "pingpong_2", .id = PINGPONG_2, > .base = 0x6b000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_1, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), > }, { > .name = "pingpong_3", .id = PINGPONG_3, > .base = 0x6c000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_1, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), > }, { > .name = "pingpong_4", .id = PINGPONG_4, > .base = 0x6d000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_2, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), > }, { > .name = "pingpong_5", .id = PINGPONG_5, > .base = 0x6e000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_2, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), > }, { > .name = "pingpong_cwb_0", .id = PINGPONG_CWB_0, > .base = 0x66000, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_3, > }, { > .name = "pingpong_cwb_1", .id = PINGPONG_CWB_1, > .base = 0x66400, .len = 0, > - .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sc7280_pp_sblk, > .merge_3d = MERGE_3D_3, > }, > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 75b679cd2bd27dd25971489a2d3a6f516b248235..4777a4a852da0d65e20cebc31fd05647e0b4c4b2 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -95,12 +95,6 @@ > #define MIXER_QCM2290_MASK \ > (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) > > -#define PINGPONG_SDM845_MASK \ > - (BIT(DPU_PINGPONG_DITHER)) > - > -#define PINGPONG_SM8150_MASK \ > - (BIT(DPU_PINGPONG_DITHER)) > - > #define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \ > BIT(DPU_WB_UBWC) | \ > BIT(DPU_WB_YUV_CONFIG) | \ > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index ac63f753b43615f7c34d2da51fce919fd77142bf..d48c26a7cb6b69961cebc19576e3f7fc3b8dd2c5 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -117,13 +117,11 @@ enum { > * PINGPONG sub-blocks > * @DPU_PINGPONG_SPLIT PP block supports split fifo > * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo > - * @DPU_PINGPONG_DITHER Dither blocks > * @DPU_PINGPONG_MAX > */ > enum { > DPU_PINGPONG_SPLIT = 0x1, > DPU_PINGPONG_SLAVE, > - DPU_PINGPONG_DITHER, > DPU_PINGPONG_MAX > }; > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c > index 49e03ecee9e8b567a3f809b977deb83731006ac0..138071be56496da9fdcaff902f68ebb09a212e2e 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c > @@ -325,7 +325,7 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(struct drm_device *dev, > c->ops.disable_dsc = dpu_hw_pp_dsc_disable; > } > > - if (test_bit(DPU_PINGPONG_DITHER, &cfg->features)) > + if (mdss_rev->core_major_ver >= 3) > c->ops.setup_dither = dpu_hw_pp_setup_dither; > > return c; > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
On 19/05/2025 18:04, Dmitry Baryshkov wrote: > From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > Continue migration to the MDSS-revision based checks and replace > DPU_DATA_HCTL_EN feature bit with the core_major_ver >= 5 check. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +-- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 2 +- > 3 files changed, 2 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 5cd87b13e839e7ad60356cde162405fdfb6f9498..1244dd59648d11123c507a1369f28f952d047fd5 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -106,8 +106,7 @@ > > #define INTF_SC7180_MASK \ > (BIT(DPU_INTF_INPUT_CTRL) | \ > - BIT(DPU_INTF_STATUS_SUPPORTED) | \ > - BIT(DPU_DATA_HCTL_EN)) > + BIT(DPU_INTF_STATUS_SUPPORTED)) > > #define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \ > BIT(DPU_WB_UBWC) | \ > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 3b6133e1bb581741fe87b049ad0c89bf30b76019..bf6b2392efb47fa8c3e3c5d17f1a72341872e18b 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -143,14 +143,11 @@ enum { > * INTF sub-blocks > * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which > * pixel data arrives to this INTF > - * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate > - * than video timing > * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register > * @DPU_INTF_MAX > */ > enum { > DPU_INTF_INPUT_CTRL = 0x1, > - DPU_DATA_HCTL_EN, > DPU_INTF_STATUS_SUPPORTED, > DPU_INTF_MAX > }; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > index 1d56c21ac79095ab515aeb485346e1eb5793c260..8f9733aad2dec3a9b5464d55b00f350348842911 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > @@ -237,7 +237,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, > DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3); > DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg); > DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format); > - if (intf->cap->features & BIT(DPU_DATA_HCTL_EN)) { > + if (intf->mdss_ver->core_major_ver >= 5) { > /* > * DATA_HCTL_EN controls data timing which can be different from > * video timing. It is recommended to enable it for all cases, except > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
On 19/05/2025 18:04, Dmitry Baryshkov wrote: > From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > Continue migration to the MDSS-revision based checks and replace > DPU_CTL_DSPP_SUB_BLOCK_FLUSH feature bit with the core_major_ver >= 7 > check. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +-- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +- > 3 files changed, 2 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 6fed2cce082c476c1f7f8ee683f2a6f3eeaa5231..19a859e2a1f80c2321789af4ec7c5e299f0fb873 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -105,8 +105,7 @@ > (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) > > #define CTL_SC7280_MASK \ > - (BIT(DPU_CTL_VM_CFG) | \ > - BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) > + (BIT(DPU_CTL_VM_CFG)) > > #define INTF_SC7180_MASK \ > (BIT(DPU_INTF_INPUT_CTRL) | \ > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 82f04de6300eca7d05ece3ac880c26f3a56505b9..1e5fc1d5873975189a1759212b8a6c6078de22f9 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -133,13 +133,11 @@ enum { > * CTL sub-blocks > * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display > * @DPU_CTL_VM_CFG: CTL config to support multiple VMs > - * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush > * @DPU_CTL_MAX > */ > enum { > DPU_CTL_SPLIT_DISPLAY = 0x1, > DPU_CTL_VM_CFG, > - DPU_CTL_DSPP_SUB_BLOCK_FLUSH, > DPU_CTL_MAX > }; > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > index 772df53bfc4fcc2ff976f66ef7339be1ae3da8f4..edb82c81b0a449b1a7273fc258961b9447be8d9d 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > @@ -804,7 +804,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev, > c->ops.setup_blendstage = dpu_hw_ctl_setup_blendstage; > c->ops.update_pending_flush_sspp = dpu_hw_ctl_update_pending_flush_sspp; > c->ops.update_pending_flush_mixer = dpu_hw_ctl_update_pending_flush_mixer; > - if (c->caps->features & BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) > + if (mdss_ver->core_major_ver >= 7) > c->ops.update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp_sub_blocks; > else > c->ops.update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp; > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
On 19/05/2025 18:04, Dmitry Baryshkov wrote: > From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > Continue migration to the MDSS-revision based checks and replace > DPU_CTL_ACTIVE_CFG feature bit with the core_major_ver >= 5 check. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> > --- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 6 ------ > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 ------ > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 6 ------ > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 6 ------ > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 6 ------ > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 6 ------ > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 3 --- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 - > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 4 ---- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 - > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 - > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 7 ++----- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +-- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 - > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +- > 17 files changed, 6 insertions(+), 57 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h > index b2ee5ee01870507d9f01020443c30dc573414c72..6c8ef23099a8212f33780d27a76991e9955a9bc3 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h > @@ -41,32 +41,26 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = { > { > .name = "ctl_0", .id = CTL_0, > .base = 0x1000, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), > }, { > .name = "ctl_1", .id = CTL_1, > .base = 0x1200, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), > }, { > .name = "ctl_2", .id = CTL_2, > .base = 0x1400, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), > }, { > .name = "ctl_3", .id = CTL_3, > .base = 0x1600, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), > }, { > .name = "ctl_4", .id = CTL_4, > .base = 0x1800, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), > }, { > .name = "ctl_5", .id = CTL_5, > .base = 0x1a00, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), > }, > }; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h > index 6db04c668a87a9f7baea01a9ea2a0f1bbb1212bf..37d18803af4b850c40ab855b1f13db96f3ee96ea 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h > @@ -41,32 +41,26 @@ static const struct dpu_ctl_cfg sc8180x_ctl[] = { > { > .name = "ctl_0", .id = CTL_0, > .base = 0x1000, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), > }, { > .name = "ctl_1", .id = CTL_1, > .base = 0x1200, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), > }, { > .name = "ctl_2", .id = CTL_2, > .base = 0x1400, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), > }, { > .name = "ctl_3", .id = CTL_3, > .base = 0x1600, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), > }, { > .name = "ctl_4", .id = CTL_4, > .base = 0x1800, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), > }, { > .name = "ctl_5", .id = CTL_5, > .base = 0x1a00, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), > }, > }; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h > index 6f61ce85c536e36b65b98ba4740711cb495a7c9a..41b43fb258508f1a5f285c88a3c1dc2f5f271cd0 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h > @@ -38,32 +38,26 @@ static const struct dpu_ctl_cfg sm7150_ctl[] = { > { > .name = "ctl_0", .id = CTL_0, > .base = 0x1000, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), > }, { > .name = "ctl_1", .id = CTL_1, > .base = 0x1200, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), > }, { > .name = "ctl_2", .id = CTL_2, > .base = 0x1400, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), > }, { > .name = "ctl_3", .id = CTL_3, > .base = 0x1600, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), > }, { > .name = "ctl_4", .id = CTL_4, > .base = 0x1800, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), > }, { > .name = "ctl_5", .id = CTL_5, > .base = 0x1a00, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), > }, > }; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h > index dc6d8fd05c2e3afbe5182b1ae8dd9fea8b6543e5..d44db988a6e2f443803a422846f817779d382b2a 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h > @@ -35,32 +35,26 @@ static const struct dpu_ctl_cfg sm6150_ctl[] = { > { > .name = "ctl_0", .id = CTL_0, > .base = 0x1000, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), > }, { > .name = "ctl_1", .id = CTL_1, > .base = 0x1200, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), > }, { > .name = "ctl_2", .id = CTL_2, > .base = 0x1400, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), > }, { > .name = "ctl_3", .id = CTL_3, > .base = 0x1600, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), > }, { > .name = "ctl_4", .id = CTL_4, > .base = 0x1800, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), > }, { > .name = "ctl_5", .id = CTL_5, > .base = 0x1a00, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), > }, > }; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h > index 192e90b570dbf8f5c3c24f572443e111f6cf3db2..6e571480c4a44b4f4663574c31270657b9a06a7a 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h > @@ -35,32 +35,26 @@ static const struct dpu_ctl_cfg sm6125_ctl[] = { > { > .name = "ctl_0", .id = CTL_0, > .base = 0x1000, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), > }, { > .name = "ctl_1", .id = CTL_1, > .base = 0x1200, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), > }, { > .name = "ctl_2", .id = CTL_2, > .base = 0x1400, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), > }, { > .name = "ctl_3", .id = CTL_3, > .base = 0x1600, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), > }, { > .name = "ctl_4", .id = CTL_4, > .base = 0x1800, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), > }, { > .name = "ctl_5", .id = CTL_5, > .base = 0x1a00, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), > }, > }; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h > index bdd92b5a61eabc6a1d5e0bfe740ed6d9f1e8e94f..6f9dc261e667fca3e94ec24e00d45f9af46e401e 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h > @@ -39,32 +39,26 @@ static const struct dpu_ctl_cfg sm8250_ctl[] = { > { > .name = "ctl_0", .id = CTL_0, > .base = 0x1000, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), > }, { > .name = "ctl_1", .id = CTL_1, > .base = 0x1200, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), > }, { > .name = "ctl_2", .id = CTL_2, > .base = 0x1400, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), > }, { > .name = "ctl_3", .id = CTL_3, > .base = 0x1600, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), > }, { > .name = "ctl_4", .id = CTL_4, > .base = 0x1800, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), > }, { > .name = "ctl_5", .id = CTL_5, > .base = 0x1a00, .len = 0x1e0, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), > }, > }; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h > index ce2ec6af5f53e2177009ca8826ca510fa08c03c7..373c7d605a04a1fc72f45e993ec176e8f5e015fe 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h > @@ -32,17 +32,14 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = { > { > .name = "ctl_0", .id = CTL_0, > .base = 0x1000, .len = 0x1dc, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), > }, { > .name = "ctl_1", .id = CTL_1, > .base = 0x1200, .len = 0x1dc, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), > }, { > .name = "ctl_2", .id = CTL_2, > .base = 0x1400, .len = 0x1dc, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), > }, > }; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h > index 986179b53f8b59200d10f5159cac630732dc7196..1cf9f99d0542cf7037d2a9672d51ca7c437c364e 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h > @@ -29,7 +29,6 @@ static const struct dpu_ctl_cfg sm6115_ctl[] = { > { > .name = "ctl_0", .id = CTL_0, > .base = 0x1000, .len = 0x1dc, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), > }, > }; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h > index c2321a4a7d3894d85062d083b45402950122007b..a3db71676f468526ea129c4b8465fb2c47885162 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h > @@ -35,22 +35,18 @@ static const struct dpu_ctl_cfg sm6350_ctl[] = { > { > .name = "ctl_0", .id = CTL_0, > .base = 0x1000, .len = 0x1dc, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), > }, { > .name = "ctl_1", .id = CTL_1, > .base = 0x1200, .len = 0x1dc, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), > }, { > .name = "ctl_2", .id = CTL_2, > .base = 0x1400, .len = 0x1dc, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), > }, { > .name = "ctl_3", .id = CTL_3, > .base = 0x1600, .len = 0x1dc, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), > }, > }; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h > index c3dd2383bd5f32926b50d98c937da25ed59d7cb3..719cfaa98ab9e735d9255d9a5f1a4275739b4b1d 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h > @@ -29,7 +29,6 @@ static const struct dpu_ctl_cfg qcm2290_ctl[] = { > { > .name = "ctl_0", .id = CTL_0, > .base = 0x1000, .len = 0x1dc, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), > }, > }; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h > index abeaa2b8e06fdf6ce5cec2c1a4fd025a342f5a2f..04cdda85e6828a83e99d146ee9d9f809f1acc007 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h > @@ -30,7 +30,6 @@ static const struct dpu_ctl_cfg sm6375_ctl[] = { > { > .name = "ctl_0", .id = CTL_0, > .base = 0x1000, .len = 0x1dc, > - .features = BIT(DPU_CTL_ACTIVE_CFG), > .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), > }, > }; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > index a0ba55ab3c894c200225fe48ec6214ae4135d059..25ba5d9bfff2b3f7a5054ae26511d05917f72d8b 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > @@ -69,7 +69,7 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( > ctl->ops.setup_intf_cfg(ctl, &intf_cfg); > > /* setup which pp blk will connect to this intf */ > - if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) && phys_enc->hw_intf->ops.bind_pingpong_blk) > + if (phys_enc->hw_intf->ops.bind_pingpong_blk) Why did you drop the version test here ? Neil > phys_enc->hw_intf->ops.bind_pingpong_blk( > phys_enc->hw_intf, > phys_enc->hw_pp->idx); > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > index d35d15b60260037c5c0c369cb061e7759243b6fd..e12bca8a26ec98565a96919b1c43f7fa2ea8a0df 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > @@ -373,7 +373,7 @@ static void dpu_encoder_phys_vid_underrun_irq(void *arg) > static bool dpu_encoder_phys_vid_needs_single_flush( > struct dpu_encoder_phys *phys_enc) > { > - return !(phys_enc->hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) && > + return !(phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5) && > phys_enc->split_role != ENC_ROLE_SOLO; > } > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c > index 849fea580a4ca55fc4a742c6b6dee7dfcdd788e4..c8f3516ae4faa709e3eda4c0efb050ca18b675e4 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c > @@ -218,7 +218,6 @@ static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc, > static void dpu_encoder_phys_wb_setup_ctl(struct dpu_encoder_phys *phys_enc) > { > struct dpu_hw_wb *hw_wb; > - struct dpu_hw_ctl *ctl; > struct dpu_hw_cdm *hw_cdm; > > if (!phys_enc) { > @@ -227,10 +226,9 @@ static void dpu_encoder_phys_wb_setup_ctl(struct dpu_encoder_phys *phys_enc) > } > > hw_wb = phys_enc->hw_wb; > - ctl = phys_enc->hw_ctl; > hw_cdm = phys_enc->hw_cdm; > > - if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) && > + if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5 && > (phys_enc->hw_ctl && > phys_enc->hw_ctl->ops.setup_intf_cfg)) { > struct dpu_hw_intf_cfg intf_cfg = {0}; > @@ -534,7 +532,6 @@ static void dpu_encoder_phys_wb_enable(struct dpu_encoder_phys *phys_enc) > static void dpu_encoder_phys_wb_disable(struct dpu_encoder_phys *phys_enc) > { > struct dpu_hw_wb *hw_wb = phys_enc->hw_wb; > - struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl; > > DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0); > > @@ -556,7 +553,7 @@ static void dpu_encoder_phys_wb_disable(struct dpu_encoder_phys *phys_enc) > * WB support is added to those targets will need to add > * the legacy teardown sequence as well. > */ > - if (hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) > + if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5) > dpu_encoder_helper_phys_cleanup(phys_enc); > > phys_enc->enable_state = DPU_ENC_DISABLED; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index a162c4f9ebd79d3ba16b50117ee7462afdbbf3d4..0863e5cfb3283ed32f61ddd4483220742df8633d 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -105,8 +105,7 @@ > (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) > > #define CTL_SC7280_MASK \ > - (BIT(DPU_CTL_ACTIVE_CFG) | \ > - BIT(DPU_CTL_FETCH_ACTIVE) | \ > + (BIT(DPU_CTL_FETCH_ACTIVE) | \ > BIT(DPU_CTL_VM_CFG) | \ > BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 3d6c2db395b65b89845cb7281195ca5ca16c22e6..9981d090b689b46bbc378d1965b0efd1df0efa8b 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -139,7 +139,6 @@ enum { > */ > enum { > DPU_CTL_SPLIT_DISPLAY = 0x1, > - DPU_CTL_ACTIVE_CFG, > DPU_CTL_FETCH_ACTIVE, > DPU_CTL_VM_CFG, > DPU_CTL_DSPP_SUB_BLOCK_FLUSH, > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > index 58bdd4d33b37d83f30931f09fdf80bef41e1f0fe..2dfb7db371a3915f663cf134e4dd62f92224185b 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > @@ -766,7 +766,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev, > c->caps = cfg; > c->mdss_ver = mdss_ver; > > - if (c->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) { > + if (mdss_ver->core_major_ver >= 5) { > c->ops.trigger_flush = dpu_hw_ctl_trigger_flush_v1; > c->ops.setup_intf_cfg = dpu_hw_ctl_intf_cfg_v1; > c->ops.reset_intf_cfg = dpu_hw_ctl_reset_intf_cfg_v1; >
On 19/05/2025 18:04, Dmitry Baryshkov wrote: > From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > Continue migration to the MDSS-revision based checks and replace > DPU_MIXER_COMBINED_ALPHA feature bit with the core_major_ver >= 4 check. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 ++-- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 6 ++++-- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 3 ++- > drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +- > 5 files changed, 9 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 4777a4a852da0d65e20cebc31fd05647e0b4c4b2..d64ebc729bfb589bf90af89c094181f879d5b1ef 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -90,10 +90,10 @@ > (BIT(DPU_MIXER_SOURCESPLIT)) > > #define MIXER_SDM845_MASK \ > - (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) > + (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER)) > > #define MIXER_QCM2290_MASK \ > - (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) > + (BIT(DPU_DIM_LAYER)) > > #define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \ > BIT(DPU_WB_UBWC) | \ > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 9ba9e273f81ab1966db1865b4ce28f8c18f750b8..5e4608d10c6d4fee387c9a599a73b15661148430 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -85,7 +85,6 @@ enum { > * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration > * @DPU_MIXER_GC Gamma correction block > * @DPU_DIM_LAYER Layer mixer supports dim layer > - * @DPU_MIXER_COMBINED_ALPHA Layer mixer has combined alpha register > * @DPU_MIXER_MAX maximum value > */ > enum { > @@ -93,7 +92,6 @@ enum { > DPU_MIXER_SOURCESPLIT, > DPU_MIXER_GC, > DPU_DIM_LAYER, > - DPU_MIXER_COMBINED_ALPHA, > DPU_MIXER_MAX > }; > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c > index 4f57cfca89bd3962e7e512952809db0300cb9baf..3bfb61cb83672dca4236bdbbbfb1e442223576d2 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c > @@ -150,10 +150,12 @@ static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx, > * @dev: Corresponding device for devres management > * @cfg: mixer catalog entry for which driver object is required > * @addr: mapped register io address of MDP > + * @mdss_ver: DPU core's major and minor versions > */ > struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev, > const struct dpu_lm_cfg *cfg, > - void __iomem *addr) > + void __iomem *addr, > + const struct dpu_mdss_version *mdss_ver) > { > struct dpu_hw_mixer *c; > > @@ -173,7 +175,7 @@ struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev, > c->idx = cfg->id; > c->cap = cfg; > c->ops.setup_mixer_out = dpu_hw_lm_setup_out; > - if (test_bit(DPU_MIXER_COMBINED_ALPHA, &c->cap->features)) > + if (mdss_ver->core_major_ver >= 4) > c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha; > else > c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h > index 6f60fa9b3cd78160699a97dc7a86a5ec0b599281..fff1156add683fec8ce6785e7fe1d769d0de3fe0 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h > @@ -95,6 +95,7 @@ static inline struct dpu_hw_mixer *to_dpu_hw_mixer(struct dpu_hw_blk *hw) > > struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev, > const struct dpu_lm_cfg *cfg, > - void __iomem *addr); > + void __iomem *addr, > + const struct dpu_mdss_version *mdss_ver); > > #endif /*_DPU_HW_LM_H */ > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c > index d728e275ac427f7849dad4f4a055c56840ca2d23..7bcb1e057b143a5512aafbd640199c8f3b436527 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c > @@ -60,7 +60,7 @@ int dpu_rm_init(struct drm_device *dev, > struct dpu_hw_mixer *hw; > const struct dpu_lm_cfg *lm = &cat->mixer[i]; > > - hw = dpu_hw_lm_init(dev, lm, mmio); > + hw = dpu_hw_lm_init(dev, lm, mmio, cat->mdss_ver); > if (IS_ERR(hw)) { > rc = PTR_ERR(hw); > DPU_ERROR("failed lm object creation: err %d\n", rc); > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
On 19/05/2025 18:04, Dmitry Baryshkov wrote: > From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > All existing PINGPONG feature bits are completely unused. Drop them from > the current codebase. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 12 ------------ > 1 file changed, 12 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 9658561c4cb653ca86094d67f7b5dc92d36d38cd..c1488a2c160b0e2ab08243a6e2bd099329ae759b 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -87,18 +87,6 @@ enum { > DPU_DSPP_MAX > }; > > -/** > - * PINGPONG sub-blocks > - * @DPU_PINGPONG_SPLIT PP block supports split fifo > - * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo > - * @DPU_PINGPONG_MAX > - */ > -enum { > - DPU_PINGPONG_SPLIT = 0x1, > - DPU_PINGPONG_SLAVE, > - DPU_PINGPONG_MAX > -}; > - > /** > * CTL sub-blocks > * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
On Tue, May 20, 2025 at 09:57:38AM +0200, neil.armstrong@linaro.org wrote: > On 19/05/2025 18:04, Dmitry Baryshkov wrote: > > From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > > > Continue migration to the MDSS-revision based checks and replace > > DPU_CTL_ACTIVE_CFG feature bit with the core_major_ver >= 5 check. > > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> > > --- > > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 6 ------ > > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 ------ > > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 6 ------ > > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 6 ------ > > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 6 ------ > > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 6 ------ > > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 3 --- > > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 - > > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 4 ---- > > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 - > > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 - > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +- > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +- > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 7 ++----- > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +-- > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 - > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +- > > 17 files changed, 6 insertions(+), 57 deletions(-) > > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > > index a0ba55ab3c894c200225fe48ec6214ae4135d059..25ba5d9bfff2b3f7a5054ae26511d05917f72d8b 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > > @@ -69,7 +69,7 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( > > ctl->ops.setup_intf_cfg(ctl, &intf_cfg); > > /* setup which pp blk will connect to this intf */ > > - if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) && phys_enc->hw_intf->ops.bind_pingpong_blk) > > + if (phys_enc->hw_intf->ops.bind_pingpong_blk) > > Why did you drop the version test here ? bind_pingpong_blk is only available since DPU 5.x, the same set of hardware as the DPU having DPU_CTL_ACTIVE_CFG.
Some time ago we started the process of converting HW blocks to use revision-based checks instead of having feature bits (which are easy to miss or to set incorrectly). Then the process of such a conversion was postponed. (Mostly) finish the conversion. The only blocks which still have feature bits are SSPP, WB and VBIF. In the rare cases where behaviour actually differs from platform to platform (or from block to block) use unsigned long bitfields, they have simpler syntax to be checked and don't involve test_bit() invocation. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> --- Changes in v4: - Rebased on top of linux-next - Dropped three controversial patches, will be submitted separately - Folded MIXER_SDM845_MASK into MIXER_MSM8998_MASK as they are equal now. - Link to v3: https://lore.kernel.org/r/20250424-dpu-drop-features-v3-0-cdaca81d356f@oss.qualcomm.com Changes in v3: - Repost, fixing email/author issues caused by b4 / mailmap interaction - Link to v2: https://lore.kernel.org/r/20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com Changes in v2: - Rebased on top of the current msm-next - Link to v1: https://lore.kernel.org/r/20241214-dpu-drop-features-v1-0-988f0662cb7e@linaro.org --- Dmitry Baryshkov (30): drm/msm/dpu: stop passing mdss_ver to setup_timing_gen() drm/msm/dpu: drop INTF_SC7280_MASK drm/msm/dpu: inline _setup_ctl_ops() drm/msm/dpu: inline _setup_dsc_ops() drm/msm/dpu: inline _setup_dspp_ops() drm/msm/dpu: inline _setup_mixer_ops() drm/msm/dpu: remove DSPP_SC7180_MASK drm/msm/dpu: get rid of DPU_CTL_HAS_LAYER_EXT4 drm/msm/dpu: get rid of DPU_CTL_ACTIVE_CFG drm/msm/dpu: get rid of DPU_CTL_FETCH_ACTIVE drm/msm/dpu: get rid of DPU_CTL_DSPP_SUB_BLOCK_FLUSH drm/msm/dpu: get rid of DPU_CTL_VM_CFG drm/msm/dpu: get rid of DPU_DATA_HCTL_EN drm/msm/dpu: get rid of DPU_INTF_STATUS_SUPPORTED drm/msm/dpu: get rid of DPU_INTF_INPUT_CTRL drm/msm/dpu: get rid of DPU_PINGPONG_DSC drm/msm/dpu: get rid of DPU_PINGPONG_DITHER drm/msm/dpu: get rid of DPU_MDP_VSYNC_SEL drm/msm/dpu: get rid of DPU_MDP_PERIPH_0_REMOVED drm/msm/dpu: get rid of DPU_MDP_AUDIO_SELECT drm/msm/dpu: get rid of DPU_MIXER_COMBINED_ALPHA drm/msm/dpu: get rid of DPU_DIM_LAYER drm/msm/dpu: get rid of DPU_DSC_HW_REV_1_2 drm/msm/dpu: get rid of DPU_DSC_OUTPUT_CTRL drm/msm/dpu: get rid of DPU_WB_INPUT_CTRL drm/msm/dpu: get rid of DPU_SSPP_QOS_8LVL drm/msm/dpu: drop unused MDP TOP features drm/msm/dpu: drop ununused PINGPONG features drm/msm/dpu: drop ununused MIXER features drm/msm/dpu: move features out of the DPU_HW_BLK_INFO .../drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 49 +++------- .../drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 2 - .../drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 2 - .../drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 2 - .../drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 7 -- .../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 7 -- .../gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 7 -- .../gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 4 - .../gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 17 +--- .../gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h | 11 +-- .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 39 ++------ .../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 43 ++------- .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 29 +----- .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 19 +--- .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 16 +--- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 38 ++------ .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 14 +-- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 5 - .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 16 +--- .../drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 5 - .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 6 -- .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 40 ++------ .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 22 +---- .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 46 ++------- .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 43 ++------- .../drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 49 ++-------- .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 43 ++------- .../drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 43 ++------- .../drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 48 ++-------- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 5 +- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 7 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 42 +-------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 102 ++------------------ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 105 ++++++++++----------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 4 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 21 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c | 5 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c | 10 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 14 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 5 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 28 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c | 5 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 5 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 11 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 8 +- 52 files changed, 256 insertions(+), 813 deletions(-) --- base-commit: de63bbeb5af60172f1dd4d45bdc897816753fa69 change-id: 20241213-dpu-drop-features-7603dc3ee189 Best regards,