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Wed, 04 Jun 2025 08:02:41 +0000 Received: from APTAIPPMTA02.qualcomm.com (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 55482eFm003893; Wed, 4 Jun 2025 08:02:41 GMT Received: from cbsp-sh-gv.ap.qualcomm.com (CBSP-SH-gv.ap.qualcomm.com [10.231.249.68]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 55482eLp003888 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 Jun 2025 08:02:40 +0000 Received: by cbsp-sh-gv.ap.qualcomm.com (Postfix, from userid 4635958) id 8FA7E40D25; Wed, 4 Jun 2025 16:02:39 +0800 (CST) From: Wenbin Yao To: catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, kishon@kernel.org, sfr@canb.auug.org.au, linux-phy@lists.infradead.org Cc: krishna.chundru@oss.qualcomm.com, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_cang@quicinc.com, qiang.yu@oss.qualcomm.com, quic_wenbyao@quicinc.com Subject: [PATCH v4 0/5] arm64: qcom: x1e80100-qcp: Add power supply and sideband signals for PCIe RC Date: Wed, 4 Jun 2025 16:02:32 +0800 Message-Id: <20250604080237.494014-1-quic_wenbyao@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=bNYWIO+Z c=1 sm=1 tr=0 ts=683ffda4 cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=6IFa9wvqVegA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=Bg7XDE4CPuCW5LNoTQ8A:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: oxCH5CblYAdxVFJljLq4RirJs-ofu0RQ X-Proofpoint-ORIG-GUID: oxCH5CblYAdxVFJljLq4RirJs-ofu0RQ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjA0MDA2MyBTYWx0ZWRfX/aDIFhGjh4lq ROf3g+FmqCt45a9ln5oLfuUyxPENEEIcMmb8Ug5pXuXc/cM5DPtA24crJFz3ZPgXR1U3VeIJMMM zHukVV8dOlVCGAP4GIm4L5YsNAFAkTcoAz5X1JItUj6VZ09dpm3oqwpQpW4LxIKO9PRDJqfWzdk So3Nx2vKCwijFxjwRLCF1MaCDtHsmyotXIhlQptyc17wOVN3s/L+Scx77KE52rvhx4nNIOijXeI 0m4BCl2GPRuaw0zHa1+hS8llPKLBv+Q/GTC1JhD4nvQCRy+sXvSSQ5ubHmD5Xo3BdyeSMEOw3Lh vWJHwBDfMSGT7d9+5rI+DXTK2flIpIHfEgE+zOgVvz1E7rhUeXPFdkqJx4gmFXLy6n+BgnPH5nt mpWYALNce4pF/8VrQXptOeiklEr/bTYGN5NbGbtlwZA0cwnQWSfgSuL1/wrQ2R60O2O8vW+9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-04_02,2025-06-03_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 phishscore=0 priorityscore=1501 suspectscore=0 mlxscore=0 impostorscore=0 spamscore=0 clxscore=1015 mlxlogscore=999 adultscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506040063 The first patch enables the PCI Power Control driver to control the power state of PCI slots. The second patch adds the bus topology of PCIe domain 3 on x1e80100 platform. The third patch adds perst, wake and clkreq sideband signals, and describe the regulators powering the rails of the PCI slots in the devicetree for PCIe3 controller and PHY device. The fourth patch adds qref supply in dts nodes of PCIe PHYs. The fifth patch requests qref supply for PCIe PHYs. The patchset has been modified based on comments and suggestions. Changes in v4: - Replace pcie3port with pcie3_port in Patch 2/5. - Add restoring the vdda-qref request for the 3th PCIe instance by reverting commit eb7a22f830f6("phy: qcom: qmp-pcie: drop bogus x1e80100 qref supply") in Patch 5/5. - Link to v3: https://lore.kernel.org/all/20250508081514.3227956-1-quic_wenbyao@quicinc.com/ Changes in v3: - Replace PCI_PWRCTL_SLOT with PCI_PWRCTRL_SLOT in Patch 1/5. - Keep the order of pinctrl-0 before pinctrl-names in Patch 3/5. - Add Patch 5/5 to request qref supply for PCIe PHYs. - Link to v2: https://lore.kernel.org/all/20250425092955.4099677-1-quic_wenbyao@quicinc.com/ Changes in v2: - Select PCI_PWRCTL_SLOT by ARCH_QCOM in arch/arm64/Kconfig.platforms in Patch 1/4. - Add an empty line before pcie3port node in Patch 2/4. - Rename regulator-pcie_12v regulator-pcie_3v3_aux and regulator-pcie_3v3 in Patch 3/4. - Add Patch 4/4 to describe qref supply of PCIe PHYs. - Link to v1: https://lore.kernel.org/all/20250320055502.274849-1-quic_wenbyao@quicinc.com/ Qiang Yu (5): arm64: Kconfig: enable PCI Power Control Slot driver for QCOM arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3 arm64: dts: qcom: x1e80100-qcp: enable pcie3 x8 slot for X1E80100-QCP arm64: dts: qcom: x1e80100-qcp: Add qref supply for PCIe PHYs phy: qcom: qmp-pcie: add x1e80100 qref supplies arch/arm64/Kconfig.platforms | 1 + arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 121 ++++++++++++++++++++++ arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 ++ drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 41 ++++++-- 4 files changed, 167 insertions(+), 7 deletions(-) base-commit: a0bea9e39035edc56a994630e6048c8a191a99d8