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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-74890083029sm7405077b3a.81.2025.06.16.15.43.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jun 2025 15:43:02 -0700 (PDT) From: Mayank Rana To: linux-pci@vger.kernel.org, will@kernel.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, andersson@kernel.org, mani@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, devicetree@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, quic_ramkri@quicinc.com, quic_shazhuss@quicinc.com, quic_msarkar@quicinc.com, quic_nitegupt@quicinc.com, Mayank Rana Subject: [PATCH v5 0/4] Add Qualcomm SA8255p based firmware managed PCIe root complex Date: Mon, 16 Jun 2025 15:42:55 -0700 Message-Id: <20250616224259.3549811-1-mayank.rana@oss.qualcomm.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjE2MDE2MiBTYWx0ZWRfX6KPQJ7O72MnJ 9T/DI7/1RZfCcPaZOOyJAd1Wg6u0kpxgBFDGzqlSuJdR+73vpHCaXLqjr/wwzgchNHDRPRiSW5Z zt5EbaBLtyz+/t89rWJ8ytSZgaDnpSy9KKPQEt7uZsTtJQDBxySG5u0e83V5gFL+6L/F5ju7Y08 JnZIuA0F22OFV2E9yu5e9KnLMbNj7r9rexruYmJ8bJ64X7ibrT54KYO2KPBYUXiZE0oq+949kVT zvU+mdCqyg1XQJJ55olMsXDqL/+7cDgMoa8VNKxYtE21fWcD/2ITR702i5vBh7nzOcbgs42SmxJ 4kScm2mEewWq+DAZ3tgGWTUKRr5v+M/abIXwm4Ydtzq93Jr4KdngsZl3NJ0C96R1gDBJvoBYH4U XUwrSwLfoNvSxUVZSylxBitBz9FgW8RAzvQrPwPuNnXrS8R5Oir3GWLMg/NvDrS5e3ipmcu9 X-Authority-Analysis: v=2.4 cv=VvEjA/2n c=1 sm=1 tr=0 ts=68509df8 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=cBYbKlKiy6JW2YU5ZBsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: wgW0ks_9S1dQS6lb3R3GtiOvclbi9gME X-Proofpoint-ORIG-GUID: wgW0ks_9S1dQS6lb3R3GtiOvclbi9gME X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-16_11,2025-06-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxscore=0 lowpriorityscore=0 spamscore=0 mlxlogscore=999 malwarescore=0 impostorscore=0 clxscore=1015 bulkscore=0 suspectscore=0 priorityscore=1501 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506160162 Based on received feedback, this patch series adds support with existing Linux qcom-pcie.c driver to get PCIe host root complex functionality on Qualcomm SA8255P auto platform. 1. Interface to allow requesting firmware to manage system resources and performing PCIe Link up (devicetree binding in terms of power domain and runtime PM APIs is used in driver) 2. SA8255P is using Synopsys Designware PCIe controller which supports MSI controller. Using existing MSI controller based functionality by exporting important pcie dwc core driver based MSI APIs, and using those from pcie-qcom.c driver. Below architecture is used on Qualcomm SA8255P auto platform to get ECAM compliant PCIe controller based functionality. Here firmware VM based PCIe driver takes care of resource management and performing PCIe link related handling (D0 and D3cold). Linux pcie-qcom.c driver uses power domain to request firmware VM to perform these operations using SCMI interface. -------------------- ┌────────────────────────┐ │ │ ┌──────────────────────┐ │ SHARED MEMORY │ ┌──────────────────────────┐ │ Firmware VM │ │ │ │ Linux VM │ │ ┌─────────┐ │ │ │ │ ┌────────────────┐ │ │ │ Drivers │ ┌──────┐ │ │ │ │ │ PCIE Qcom │ │ │ │ PCIE PHY◄─┤ │ │ │ ┌────────────────┐ │ │ │ driver │ │ │ │ │ │ SCMI │ │ │ │ │ │ │ │ │ │ │ │PCIE CTL │ │ │ ├─────────┼───► PCIE ◄───┼─────┐ │ └──┬──────────▲──┘ │ │ │ ├─►Server│ │ │ │ SHMEM │ │ │ │ │ │ │ │ │Clk, Vreg│ │ │ │ │ │ │ │ │ │ ┌──▼──────────┴──┐ │ │ │GPIO,GDSC│ └─▲──┬─┘ │ │ └────────────────┘ │ └──────┼────┤PCIE SCMI Inst │ │ │ └─────────┘ │ │ │ │ │ │ └──▲──────────┬──┘ │ │ │ │ │ │ │ │ │ │ │ └───────────────┼──┼───┘ │ │ └───────┼──────────┼───────┘ │ │ │ │ │ │ │ │ └────────────────────────┘ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │ │IRQ │HVC IRQ │ │HVC │ │ │ │ │ │ │ │ │ │ │ │ │ │ ┌─────────────────┴──▼───────────────────────────────────────────────────────────┴──────────▼──────────────┐ │ │ │ │ │ HYPERVISOR │ │ │ │ │ │ │ └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ ┌─────────────┐ ┌─────────────┐ ┌──────────┐ ┌───────────┐ ┌─────────────┐ ┌────────────┐ │ │ │ │ │ │ │ │ │ PCIE │ │ PCIE │ │ CLOCK │ │ REGULATOR │ │ GPIO │ │ GDSC │ │ PHY │ │ controller │ └─────────────┘ └─────────────┘ └──────────┘ └───────────┘ └─────────────┘ └────────────┘ ----------------- Changes in v5: - Rebased changes to v6.16-rc1 kernel and updated proposed changes to accomodate new refactoring with pci-host-common.c file Link to v4: https://patchwork.kernel.org/project/linux-pci/cover/20250522001425.1506240-1-mayank.rana@oss.qualcomm.com/ Changes in v4: - Addressed provided review comments from reviewers Link to v3: https://lore.kernel.org/lkml/20241106221341.2218416-1-quic_mrana@quicinc.com/ Changes in v3: - Drop usage of PCIE host generic driver usage, and splitting of MSI functionality - Modified existing pcie-qcom.c driver to add support for getting ECAM compliant and firmware managed PCIe root complex functionality Link to v2: https://lore.kernel.org/linux-arm-kernel/925d1eca-975f-4eec-bdf8-ca07a892361a@quicinc.com/T/ Changes in v2: - Drop new PCIe Qcom ECAM driver, and use existing PCIe designware based MSI functionality - Add power domain based functionality within existing ECAM driver Link to v1: https://lore.kernel.org/all/d10199df-5fb3-407b-b404-a0a4d067341f@quicinc.com/T/ Tested: - Validated NVME functionality with PCIe1 on SA8255P-RIDE platform Mayank Rana (4): PCI: dwc: Export dwc MSI controller related APIs PCI: host-generic: Rename and export gen_pci_init() to allow ECAM creation dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root complex PCI: qcom: Add support for Qualcomm SA8255p based PCIe root complex .../bindings/pci/qcom,pcie-sa8255p.yaml | 122 ++++++++++++++++++ drivers/pci/controller/dwc/Kconfig | 1 + .../pci/controller/dwc/pcie-designware-host.c | 38 +++--- drivers/pci/controller/dwc/pcie-designware.h | 14 ++ drivers/pci/controller/dwc/pcie-qcom.c | 116 +++++++++++++++-- drivers/pci/controller/pci-host-common.c | 5 +- drivers/pci/controller/pci-host-common.h | 2 + 7 files changed, 269 insertions(+), 29 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml