| Message ID | cover.1606150259.git.saiprakash.ranjan@codeaurora.org |
|---|---|
| Headers | show |
| Series | System Cache support for GPU and required SMMU support | expand |
On Mon, Nov 23, 2020 at 10:35:55PM +0530, Sai Prakash Ranjan wrote: > Add iommu domain attribute for pagetable configuration which > initially will be used to set quirks like for system cache aka > last level cache to be used by client drivers like GPU to set > right attributes for caching the hardware pagetables into the > system cache and later can be extended to include other page > table configuration data. > > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > --- > drivers/iommu/arm/arm-smmu/arm-smmu.c | 20 ++++++++++++++++++++ > drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + > include/linux/io-pgtable.h | 4 ++++ > include/linux/iommu.h | 1 + > 4 files changed, 26 insertions(+) Given that we're heading for a v10 to address my comments on patch 3, then I guess you may as well split this into two patches so that I can share just the atttibute with Rob rather than the driver parts. Please keep it all as one series though, with the common parts at the beginning, and I'll figure it out. Will
On 2020-11-25 03:11, Will Deacon wrote: > On Mon, Nov 23, 2020 at 10:35:55PM +0530, Sai Prakash Ranjan wrote: >> Add iommu domain attribute for pagetable configuration which >> initially will be used to set quirks like for system cache aka >> last level cache to be used by client drivers like GPU to set >> right attributes for caching the hardware pagetables into the >> system cache and later can be extended to include other page >> table configuration data. >> >> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> >> --- >> drivers/iommu/arm/arm-smmu/arm-smmu.c | 20 ++++++++++++++++++++ >> drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + >> include/linux/io-pgtable.h | 4 ++++ >> include/linux/iommu.h | 1 + >> 4 files changed, 26 insertions(+) > > Given that we're heading for a v10 to address my comments on patch 3, > then I guess you may as well split this into two patches so that I can > share just the atttibute with Rob rather than the driver parts. > > Please keep it all as one series though, with the common parts at the > beginning, and I'll figure it out. > Ok I will split up and send v10. Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Some hardware variants contain a system cache or the last level cache(llc). This cache is typically a large block which is shared by multiple clients on the SOC. GPU uses the system cache to cache both the GPU data buffers(like textures) as well the SMMU pagetables. This helps with improved render performance as well as lower power consumption by reducing the bus traffic to the system memory. The system cache architecture allows the cache to be split into slices which then be used by multiple SOC clients. This patch series is an effort to enable and use two of those slices preallocated for the GPU, one for the GPU data buffers and another for the GPU SMMU hardware pagetables. Patch 1 - Patch 6 adds system cache support in SMMU and GPU driver. Patch 7 and 8 are minor cleanups for arm-smmu impl. Changes in v9: * Change name from domain_attr_io_pgtbl_cfg to io_pgtable_domain_attr (Will) * Modify comment for the quirk as suggested (Will) * Compare with IO_PGTABLE_QUIRK_NON_STRICT for non-strict mode (Will) Changes in v8: * Introduce a generic domain attribute for pagetable config (Will) * Rename quirk to more generic IO_PGTABLE_QUIRK_ARM_OUTER_WBWA (Will) * Move non-strict mode to use new struct domain_attr_io_pgtbl_config (Will) Changes in v7: * Squash Jordan's patch to support MMU500 targets * Rebase on top of for-joerg/arm-smmu/updates and Jordan's short series for adreno-smmu impl Changes in v6: * Move table to arm-smmu-qcom (Robin) Changes in v5: * Drop cleanup of blank lines since it was intentional (Robin) * Rebase again on top of msm-next-pgtables as it moves pretty fast Changes in v4: * Drop IOMMU_SYS_CACHE prot flag * Rebase on top of https://gitlab.freedesktop.org/drm/msm/-/tree/msm-next-pgtables Changes in v3: * Fix domain attribute setting to before iommu_attach_device() * Fix few code style and checkpatch warnings * Rebase on top of Jordan's latest split pagetables and per-instance pagetables support Changes in v2: * Addressed review comments and rebased on top of Jordan's split pagetables series Jordan Crouse (1): drm/msm/a6xx: Add support for using system cache on MMU500 based targets Sai Prakash Ranjan (5): iommu/io-pgtable-arm: Add support to use system cache iommu/arm-smmu: Add domain attribute for pagetable configuration iommu/arm-smmu: Move non-strict mode to use io_pgtable_domain_attr iommu: arm-smmu-impl: Use table to list QCOM implementations iommu: arm-smmu-impl: Add a space before open parenthesis Sharat Masetty (2): drm/msm: rearrange the gpu_rmw() function drm/msm/a6xx: Add support for using system cache(LLC) drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 109 +++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 5 + drivers/gpu/drm/msm/adreno/adreno_gpu.c | 17 ++++ drivers/gpu/drm/msm/msm_drv.c | 8 ++ drivers/gpu/drm/msm/msm_drv.h | 1 + drivers/gpu/drm/msm/msm_gpu.h | 5 +- drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 11 +-- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 21 +++- drivers/iommu/arm/arm-smmu/arm-smmu.c | 26 ++++- drivers/iommu/arm/arm-smmu/arm-smmu.h | 3 +- drivers/iommu/io-pgtable-arm.c | 10 +- include/linux/io-pgtable.h | 8 ++ include/linux/iommu.h | 1 + 13 files changed, 199 insertions(+), 26 deletions(-) base-commit: a29bbb0861f487a5e144dc997a9f71a36c7a2404