From patchwork Tue Sep 23 23:51:20 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 37775 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ee0-f69.google.com (mail-ee0-f69.google.com [74.125.83.69]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 1AEB220970 for ; Tue, 23 Sep 2014 23:52:03 +0000 (UTC) Received: by mail-ee0-f69.google.com with SMTP id e53sf63391eek.8 for ; Tue, 23 Sep 2014 16:52:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=vXCwx1ypQPt2MOtmBFMVB+AVY5N4ClMU3Bi+cM7C93I=; b=X4hekFdENmhOCCJDkz14RqOXEvXoUil26zB+/g3NhK3x88Y3m1ivG7lRt5PsxRT8Q5 9BE+xIvrvVCQICh2nWGZTaqXMe8eLWH5tQQt5ZM+sgnrGmSS0mAgfve7XB9CRynJll4M MoDlOyODtBr2FEQXJlCbftSr0WFyw9TUMIq360Vb3W8YCckWKo0PN3AnvCzkOvIsx+6x +1KDIgO8vpekHtj7w3QwzVhKkiiTUxv2K0PmP6vKCN0+NbuELsLOy72HvgldBWCFUQUm EKr/pMYW9F+Bt+9n2CN0/oeqgNA//T/fnFeOkLMo1BLLbJtwEkVs2F8geDka1Ro+4ok3 fL6g== X-Gm-Message-State: ALoCoQmsV0QQE+y4qDzAi6VR4LaPgeDi7dYaHXLTQ/6RkRrWCJDUcK61C9xwerAQE0LpsRebNmZV X-Received: by 10.180.183.165 with SMTP id en5mr3469468wic.1.1411516322253; Tue, 23 Sep 2014 16:52:02 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.43.50 with SMTP id t18ls95267lal.104.gmail; Tue, 23 Sep 2014 16:52:01 -0700 (PDT) X-Received: by 10.112.14.199 with SMTP id r7mr2680822lbc.58.1411516321874; Tue, 23 Sep 2014 16:52:01 -0700 (PDT) Received: from mail-lb0-f175.google.com (mail-lb0-f175.google.com [209.85.217.175]) by mx.google.com with ESMTPS id we6si20613033lbb.77.2014.09.23.16.52.01 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 23 Sep 2014 16:52:01 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.175 as permitted sender) client-ip=209.85.217.175; Received: by mail-lb0-f175.google.com with SMTP id w7so4113306lbi.34 for ; Tue, 23 Sep 2014 16:52:01 -0700 (PDT) X-Received: by 10.112.130.168 with SMTP id of8mr2628510lbb.5.1411516321801; Tue, 23 Sep 2014 16:52:01 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.130.169 with SMTP id of9csp501396lbb; Tue, 23 Sep 2014 16:52:00 -0700 (PDT) X-Received: by 10.68.209.169 with SMTP id mn9mr3773864pbc.37.1411516318687; Tue, 23 Sep 2014 16:51:58 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id gx10si7875646pbd.20.2014.09.23.16.51.58 for ; Tue, 23 Sep 2014 16:51:58 -0700 (PDT) Received-SPF: none (google.com: linux-arm-msm-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932376AbaIWXv5 (ORCPT + 5 others); Tue, 23 Sep 2014 19:51:57 -0400 Received: from mail-pa0-f52.google.com ([209.85.220.52]:62645 "EHLO mail-pa0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932337AbaIWXv4 (ORCPT ); Tue, 23 Sep 2014 19:51:56 -0400 Received: by mail-pa0-f52.google.com with SMTP id hz1so7486650pad.39 for ; Tue, 23 Sep 2014 16:51:55 -0700 (PDT) X-Received: by 10.66.161.41 with SMTP id xp9mr4076770pab.120.1411516315640; Tue, 23 Sep 2014 16:51:55 -0700 (PDT) Received: from ubuntu.localdomain (proxy6-global253.qualcomm.com. [199.106.103.253]) by mx.google.com with ESMTPSA id ix1sm13033521pbc.60.2014.09.23.16.51.53 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 23 Sep 2014 16:51:54 -0700 (PDT) From: Lina Iyer To: galak@codeaurora.org, sboyd@codeaurora.org, daniel.lezcano@linaro.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: khilman@linaro.org, msivasub@codeaurora.org, lorenzo.pieralisi@arm.com, linux-pm@vger.kernel.org, Lina Iyer Subject: [PATCH v6 4/5] qcom: cpuidle: Add cpuidle driver for QCOM cpus Date: Tue, 23 Sep 2014 17:51:20 -0600 Message-Id: <1411516281-58328-5-git-send-email-lina.iyer@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1411516281-58328-1-git-send-email-lina.iyer@linaro.org> References: <1411516281-58328-1-git-send-email-lina.iyer@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: lina.iyer@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.175 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add cpuidle driver interface to allow cpus to go into C-States. Use the cpuidle DT interface common across ARM architectures to provide the C-State information to the cpuidle framework. Supported modes at this time are clock gating (wfi) and cpu power down (Standalone PC or spc). Signed-off-by: Lina Iyer --- .../bindings/arm/msm/qcom,idle-state.txt | 72 +++++++++++++++++ drivers/cpuidle/Kconfig.arm | 7 ++ drivers/cpuidle/Makefile | 1 + drivers/cpuidle/cpuidle-qcom.c | 89 ++++++++++++++++++++++ 4 files changed, 169 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt create mode 100644 drivers/cpuidle/cpuidle-qcom.c diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt b/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt new file mode 100644 index 0000000..47095b9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt @@ -0,0 +1,72 @@ +QCOM Idle States for cpuidle driver + +ARM provides idle-state node to define the cpuidle states, as defined in [1]. +cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle +states. Idle states have different enter/exit latency and residency values. +The idle states supported by the QCOM SoC are defined as - + + * WFI + * Retention + * Standalone Power Collapse (Standalone PC or SPC) + * Power Collapse (PC) + +WFI: WFI does a little more in addition to architectural clock gating. ARM +processors when execute the wfi instruction will gate their internal clocks. +QCOM cpus use this instruction as a trigger for the SPM state machine. Usually +with a cpu entering WFI, the SPM is configured to do clock-gating as well. The +SPM state machine waits for the interrrupt to trigger the core back in to +active. When all CPUs in the SoC, clock gate using the ARM wfi instruction, the +second level cache usually can also clock gate sensing no cpu activity. When a +cpu is ready to run, it needs the cache to be active before starting execution. +Allowing the SPM to execute the clock gating statemachine and waiting for +interrupt on behalf of the processor has a benefit of guaranteeing that the +system state is conducive for the core to resume execution. + +Retention: Retention is a low power state where the core is clockgated and the +memory and the registers associated with the core are retained. The voltage +may be reduced to the minimum value needed to keep the processor registers +active. Retention is triggered when the core executes wfi instruction. The SPM +should be configured to execute the retention sequence and would wait for +interrupt, before restoring the cpu to execution state. Retention may have a +slightly higher latency than WFI. + +Standalone PC: A cpu can power down and warmboot if there is a sufficient time +between now and the next know wake up. SPC mode is used to indicate a core +entering a power down state without consulting any other cpu or the system +resources. This helps save power only on that core. Like WFI and Retention, the +core executes wfi and the SPM programmed to do SPC would use the cpu control +logic to power down the core's supply and restore it back when woken up by an +interrupt. Applying power and reseting the core causes the core to warmboot +back into secure mode which trampolines the control back to the kernel. To +enter a power down state the kernel needs to call into the secure layer which +would then execute the ARM wfi instruction. Failing to do so, would result in a +crash enforced by the warm boot code in the secure layer. On a SoC with +write-back L1 cache, the cache would need to be flushed. + +Power Collapse: This state is similiar to the SPC mode, but distinguishes +itself in the fact that the cpu acknowledges and permits the SoC to enter +deeper sleep modes. In a hierarchical power domain SoC, this means L2 and other +caches can be flushed, system bus, clocks - lowered, and SoC main XO turned off +and voltages reduced, provided all cpus enter this state. In other words, it is +a coupled idle state. Since the span of low power modes possible at this state +is vast, the exit latency and the residency of this low power mode would be +considered high even though at a cpu level, this essentially is cpu power down. +The SPM in this state also may handshake with the Resource power manager +processor in the SoC to indicate a complete subsystem shut down. + +The idle-state for QCOM SoCs are distinguished by the compatible property of +the node. They indicate to the cpuidle driver the entry point to use for +cpuidle. The devicetree representation of the idle state should be - + +Required properties: + +- compatible: Must be "arm,idle-state" + and one of - + "qcom,idle-state-wfi", + "qcom,idle-state-ret", + "qcom,idle-state-spc", + "qcom,idle-state-pc", + +Other required and optional properties are specified in [1]. + +[1]. Documentation/devicetree/bindings/arm/idle-states.txt diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm index 38cff69..6a9ee12 100644 --- a/drivers/cpuidle/Kconfig.arm +++ b/drivers/cpuidle/Kconfig.arm @@ -62,3 +62,10 @@ config ARM_MVEBU_V7_CPUIDLE depends on ARCH_MVEBU help Select this to enable cpuidle on Armada 370, 38x and XP processors. + +config ARM_QCOM_CPUIDLE + bool "CPU Idle drivers for Qualcomm processors" + depends on QCOM_PM + select DT_IDLE_STATES + help + Select this to enable cpuidle for QCOM processors diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile index 4d177b9..6c222d5 100644 --- a/drivers/cpuidle/Makefile +++ b/drivers/cpuidle/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_ARM_ZYNQ_CPUIDLE) += cpuidle-zynq.o obj-$(CONFIG_ARM_U8500_CPUIDLE) += cpuidle-ux500.o obj-$(CONFIG_ARM_AT91_CPUIDLE) += cpuidle-at91.o obj-$(CONFIG_ARM_EXYNOS_CPUIDLE) += cpuidle-exynos.o +obj-$(CONFIG_ARM_QCOM_CPUIDLE) += cpuidle-qcom.o ############################################################################### # MIPS drivers diff --git a/drivers/cpuidle/cpuidle-qcom.c b/drivers/cpuidle/cpuidle-qcom.c new file mode 100644 index 0000000..d226ac1 --- /dev/null +++ b/drivers/cpuidle/cpuidle-qcom.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2014, Linaro Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include + +#include +#include "dt_idle_states.h" + +static void (*qcom_idle_enter)(enum msm_pm_sleep_mode); + +static int qcom_lpm_enter_wfi(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) +{ + qcom_idle_enter(MSM_PM_SLEEP_MODE_WFI); + + return index; +} + +static int qcom_lpm_enter_spc(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) +{ + cpu_pm_enter(); + qcom_idle_enter(MSM_PM_SLEEP_MODE_SPC); + cpu_pm_exit(); + + return index; +} + +static struct cpuidle_driver qcom_cpuidle_driver = { + .name = "qcom_cpuidle", + .owner = THIS_MODULE, +}; + +static const struct of_device_id qcom_idle_state_match[] __initconst = { + { .compatible = "qcom,idle-state-wfi", .data = qcom_lpm_enter_wfi }, + { .compatible = "qcom,idle-state-spc", .data = qcom_lpm_enter_spc }, + { }, +}; + +static int qcom_cpuidle_probe(struct platform_device *pdev) +{ + struct cpuidle_driver *drv = &qcom_cpuidle_driver; + int ret; + + qcom_idle_enter = (void *)(pdev->dev.platform_data); + if (!qcom_idle_enter) + return -EFAULT; + + /* Probe for other states including platform WFI */ + ret = dt_init_idle_driver(drv, qcom_idle_state_match, 0); + if (ret <= 0) { + pr_err("%s: No cpuidle state found.\n", __func__); + return ret; + } + + ret = cpuidle_register(drv, NULL); + if (ret) { + pr_err("%s: failed to register cpuidle driver\n", __func__); + return ret; + } + + return 0; +} + +static struct platform_driver qcom_cpuidle_plat_driver = { + .probe = qcom_cpuidle_probe, + .driver = { + .name = "qcom_cpuidle", + .owner = THIS_MODULE, + }, +}; + +module_platform_driver(qcom_cpuidle_plat_driver);