diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml
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+++ b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml
@@ -0,0 +1,177 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,sm8550-iris.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm IRIS video encode and decode accelerators
+
+maintainers:
+  - Vikash Garodia <quic_vgarodia@quicinc.com>
+  - Dikshita Agarwal <quic_dikshita@quicinc.com>
+
+description:
+  The Iris video processing unit is a video encode and decode accelerator
+  present on Qualcomm platforms.
+
+properties:
+  compatible:
+    oneOf:
+      - enum:
+          - qcom,sm8550-iris
+
+  reg:
+    maxItems: 2
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    minItems: 2
+    maxItems: 4
+
+  power-domain-names:
+    oneOf:
+      - items:
+          - const: iris-ctl
+          - const: vcodec
+          - const: mxc
+          - const: mmcx
+
+  operating-points-v2: true
+
+  clocks:
+    maxItems: 3
+
+  clock-names:
+    items:
+      - const: gcc_video_axi0
+      - const: core_clk
+      - const: vcodec_core
+
+  interconnects:
+    maxItems: 2
+
+  interconnect-names:
+    items:
+      - const: iris-cnoc
+      - const: iris-ddr
+
+  memory-region:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  reset-names:
+    items:
+      - const: video_axi_reset
+
+  iommus:
+    maxItems: 2
+
+  dma-coherent: true
+
+  opp-table:
+    type: object
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - power-domain-names
+  - clocks
+  - clock-names
+  - interconnects
+  - interconnect-names
+  - memory-region
+  - resets
+  - reset-names
+  - iommus
+  - dma-coherent
+  - opp-table
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/clock/qcom,sm8550-gcc.h>
+    #include <dt-bindings/clock/qcom,sm8450-videocc.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interconnect/qcom,icc.h>
+    #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
+
+    iris: video-codec@aa00000 {
+        compatible = "qcom,sm8550-iris";
+
+        reg = <0 0x0aa00000 0 0xf0000>;
+        interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+        power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
+                        <&videocc VIDEO_CC_MVS0_GDSC>,
+                        <&rpmhpd SM8550_MXC>,
+                        <&rpmhpd SM8550_MMCX>;
+        power-domain-names = "iris-ctl", "vcodec", "mxc", "mmcx";
+        operating-points-v2 = <&iris_opp_table>;
+
+        clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+                 <&videocc VIDEO_CC_MVS0C_CLK>,
+                 <&videocc VIDEO_CC_MVS0_CLK>;
+        clock-names = "gcc_video_axi0", "core_clk", "vcodec_core";
+
+        interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+                         &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ALWAYS>,
+                        <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS
+                         &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+        interconnect-names = "iris-cnoc", "iris-ddr";
+
+        /* FW load region */
+        memory-region = <&video_mem>;
+
+        resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
+        reset-names = "video_axi_reset";
+
+        iommus = <&apps_smmu 0x1940 0x0000>,
+                 <&apps_smmu 0x1947 0x0000>;
+        dma-coherent;
+
+        status = "disabled";
+
+        iris_opp_table: opp-table {
+            compatible = "operating-points-v2";
+
+            opp-240000000 {
+                opp-hz = /bits/ 64 <240000000>;
+                required-opps = <&rpmhpd_opp_svs>,
+                                <&rpmhpd_opp_low_svs>;
+           };
+
+           opp-338000000 {
+               opp-hz = /bits/ 64 <338000000>;
+               required-opps = <&rpmhpd_opp_svs>,
+                               <&rpmhpd_opp_svs>;
+           };
+
+           opp-366000000 {
+               opp-hz = /bits/ 64 <366000000>;
+               required-opps = <&rpmhpd_opp_svs_l1>,
+                               <&rpmhpd_opp_svs_l1>;
+           };
+
+           opp-444000000 {
+               opp-hz = /bits/ 64 <444000000>;
+               required-opps = <&rpmhpd_opp_turbo>,
+                               <&rpmhpd_opp_turbo>;
+           };
+
+           opp-533333334 {
+               opp-hz = /bits/ 64 <533333334>;
+               required-opps = <&rpmhpd_opp_turbo_l1>,
+                               <&rpmhpd_opp_turbo_l1>;
+           };
+       };
+    };
+...
