From patchwork Mon Jan 28 11:53:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 156721 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3336283jaa; Mon, 28 Jan 2019 03:56:12 -0800 (PST) X-Google-Smtp-Source: ALg8bN5GcYuwvp/S9+C5ymV82YPkR9zqAOjf/3cTpxorK3subFFPyNsJCCCadgpwzZDr+8jHL73J X-Received: by 2002:a63:381c:: with SMTP id f28mr19564604pga.330.1548676572456; Mon, 28 Jan 2019 03:56:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1548676572; cv=none; d=google.com; s=arc-20160816; b=A2YHUtGzaKWbrAf06HO2FhUlSNNNw4ewO+UQK818K/Am3qhsZGfuktfCO0sL0+P5wX oG1wcpwfEzm3u9M4yDfFxeW5pRFPokwJPGteagpKdSCQ+rwOudFQAYlDXLU23sn4+M7b EJI1KrkEifaH5Cn4MX7q2fFmx4DySnYyZmm7ItQWP0n6Fd93NNHLR39aaM5KF9eLQYvQ 1goGDf+l4uyK5y49FJ1ohavEPSgO9Ud1dDD0qkwPK7jpYCdrQnWklzuHWzQ+LfwRcHIp mtHTNw/a8ebbeJNfW2Zm5P7MM/PCs+FwwfaPGTR5fhIHG8RsMsfzdE9YFIbiX1f8Dy2s M/lQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=Bae/i4n5xPawonlX2VD+cpf+OtaGJ4nCPJezQHllRaU=; b=E/4Vv3u2elqKxYkK9nKG1i2N513Do9pWtGCAwNOgtU74HGVUVk5NEmRDGFC9UY9vE7 o6NA5c6/kT6o2DDSm2Pfii8iEThF+LOnWs7ssuTN5+VG9UciSTfhLbLV59lRlxjgzhXc lZbTP61gjMXo1e0IijxvAiQg0tXHOXTpwSOxBqO+YGjv/2bcDhecP5Chvv+9GYCiGQCZ bY1lmuieaSRIs2oFAklbTkaDTrIwVD57+UozsueUPbIgOKwxnTlu+7oyccj3o7a0VoiN SnTiBxsED3C6JVIfRswP4mgDpFfJVzoBpFIwrCYWF83+nBfIIl92QWWA5/JtAbQjgE1w h0zQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=FlW51fWd; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r11si32668924plo.319.2019.01.28.03.56.11; Mon, 28 Jan 2019 03:56:12 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=FlW51fWd; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726714AbfA1L4L (ORCPT + 15 others); Mon, 28 Jan 2019 06:56:11 -0500 Received: from mail.kernel.org ([198.145.29.99]:34210 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726611AbfA1L4K (ORCPT ); Mon, 28 Jan 2019 06:56:10 -0500 Received: from localhost.localdomain (unknown [106.200.228.251]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 5E7BE2086C; Mon, 28 Jan 2019 11:56:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1548676569; bh=559CPLfcG5St/5z9rJpZ8EVehSIrsJuSZjAHbs7bDY0=; h=From:To:Cc:Subject:Date:From; b=FlW51fWdpwmWeOkpHsDAmIJLbYWPa1GmefF70qwvSc8bWa5n6Joi2B68D+I9PzupT SZQI09SNjhbL1ml4xf7VDZmeLMWTOVpNYwEkM2UZ8kBJBvXPnrjKu9qULnUEud2IOo 9TuRz+vX0FA0feL4A5ULgm7XnQjL800MwfRool9w= From: Vinod Koul To: Michael Turquette , Stephen Boyd Cc: Khasim Syed Mohammed , Bjorn Andersson , Taniya Das , Andy Gross , David Brown , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Anu Ramanathan , Shawn Guo , Vinod Koul Subject: [PATCH 1/2] clk: qcom: clk-rcg2: Introduce a cfg offset for RCGs Date: Mon, 28 Jan 2019 17:23:58 +0530 Message-Id: <20190128115359.30039-1-vkoul@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Taniya Das The RCG CFG/M/N/D register base could be at a different offset than the CMD register, so introduce a cfg_offset to identify the offset with respect to the CMD register. Signed-off-by: Taniya Das Signed-off-by: Anu Ramanathan Signed-off-by: Shawn Guo Signed-off-by: Vinod Koul --- drivers/clk/qcom/clk-rcg.h | 2 ++ drivers/clk/qcom/clk-rcg2.c | 30 +++++++++++++++++++----------- 2 files changed, 21 insertions(+), 11 deletions(-) -- 2.20.1 diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index e5eca8a1abe4..f06783c20688 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -140,6 +140,7 @@ extern const struct clk_ops clk_dyn_rcg_ops; * @parent_map: map from software's parent index to hardware's src_sel field * @freq_tbl: frequency table * @clkr: regmap clock handle + * @cfg_off: defines the cfg register offset from the CMD_RCGR * */ struct clk_rcg2 { @@ -150,6 +151,7 @@ struct clk_rcg2 { const struct parent_map *parent_map; const struct freq_tbl *freq_tbl; struct clk_regmap clkr; + u8 cfg_off; }; #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 6e3bd195d012..106848e3313f 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -74,7 +74,8 @@ static u8 clk_rcg2_get_parent(struct clk_hw *hw) u32 cfg; int i, ret; - ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); + ret = regmap_read(rcg->clkr.regmap, + rcg->cmd_rcgr + rcg->cfg_off + CFG_REG, &cfg); if (ret) goto err; @@ -123,7 +124,8 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index) int ret; u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; - ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, + ret = regmap_update_bits(rcg->clkr.regmap, + rcg->cmd_rcgr + rcg->cfg_off + CFG_REG, CFG_SRC_SEL_MASK, cfg); if (ret) return ret; @@ -162,13 +164,16 @@ clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) struct clk_rcg2 *rcg = to_clk_rcg2(hw); u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask; - regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); + regmap_read(rcg->clkr.regmap, + rcg->cmd_rcgr + rcg->cfg_off + CFG_REG, &cfg); if (rcg->mnd_width) { mask = BIT(rcg->mnd_width) - 1; - regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG, &m); + regmap_read(rcg->clkr.regmap, + rcg->cmd_rcgr + rcg->cfg_off + M_REG, &m); m &= mask; - regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG, &n); + regmap_read(rcg->clkr.regmap, + rcg->cmd_rcgr + rcg->cfg_off + N_REG, &n); n = ~n; n &= mask; n += m; @@ -263,17 +268,20 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) if (rcg->mnd_width && f->n) { mask = BIT(rcg->mnd_width) - 1; ret = regmap_update_bits(rcg->clkr.regmap, - rcg->cmd_rcgr + M_REG, mask, f->m); + rcg->cmd_rcgr + rcg->cfg_off + M_REG, + mask, f->m); if (ret) return ret; ret = regmap_update_bits(rcg->clkr.regmap, - rcg->cmd_rcgr + N_REG, mask, ~(f->n - f->m)); + rcg->cmd_rcgr + rcg->cfg_off + N_REG, + mask, ~(f->n - f->m)); if (ret) return ret; ret = regmap_update_bits(rcg->clkr.regmap, - rcg->cmd_rcgr + D_REG, mask, ~f->n); + rcg->cmd_rcgr + rcg->cfg_off + D_REG, + mask, ~f->n); if (ret) return ret; } @@ -284,9 +292,9 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; if (rcg->mnd_width && f->n && (f->m != f->n)) cfg |= CFG_MODE_DUAL_EDGE; - - return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, - mask, cfg); + return regmap_update_bits(rcg->clkr.regmap, + rcg->cmd_rcgr + rcg->cfg_off + CFG_REG, + mask, cfg); } static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)