diff mbox series

[v2,25/40] PCI: dwc/meson: Drop the duplicate number of lanes setup

Message ID 20200821035420.380495-26-robh@kernel.org
State Accepted
Commit 244c40cc28b116b6530a6d9b24ac290e0f89607c
Headers show
Series [v2,01/40] PCI: Allow root and child buses to have different pci_ops | expand

Commit Message

Rob Herring (Arm) Aug. 21, 2020, 3:54 a.m. UTC 
The meson lanes initialization is the same DWC port logic registers as
in dw_pcie_setup(). We just need to initialize 'num_lanes' to 1 to do
the same init.

dw_pcie_setup_rc() sets the PORT_LOGIC_SPEED_CHANGE bit, so setting it
can be dropped.

Cc: Yue Wang <yue.wang@Amlogic.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Jerome Brunet <jbrunet@baylibre.com>
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: linux-amlogic@lists.infradead.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
 drivers/pci/controller/dwc/pci-meson.c | 29 +-------------------------
 1 file changed, 1 insertion(+), 28 deletions(-)
diff mbox series

Patch

diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c
index 67ca73528aad..96308743faf4 100644
--- a/drivers/pci/controller/dwc/pci-meson.c
+++ b/drivers/pci/controller/dwc/pci-meson.c
@@ -22,18 +22,6 @@ 
 
 #define to_meson_pcie(x) dev_get_drvdata((x)->dev)
 
-/* External local bus interface registers */
-#define PLR_OFFSET			0x700
-#define PCIE_PORT_LINK_CTRL_OFF		(PLR_OFFSET + 0x10)
-#define FAST_LINK_MODE			BIT(7)
-#define LINK_CAPABLE_MASK		GENMASK(21, 16)
-#define LINK_CAPABLE_X1			BIT(16)
-
-#define PCIE_GEN2_CTRL_OFF		(PLR_OFFSET + 0x10c)
-#define NUM_OF_LANES_MASK		GENMASK(12, 8)
-#define NUM_OF_LANES_X1			BIT(8)
-#define DIRECT_SPEED_CHANGE		BIT(17)
-
 #define TYPE1_HDR_OFFSET		0x0
 #define PCIE_STATUS_COMMAND		(TYPE1_HDR_OFFSET + 0x04)
 #define PCI_IO_EN			BIT(0)
@@ -288,22 +276,6 @@  static void meson_pcie_init_dw(struct meson_pcie *mp)
 	val |= APP_LTSSM_ENABLE;
 	meson_cfg_writel(mp, val, PCIE_CFG0);
 
-	val = meson_elb_readl(mp, PCIE_PORT_LINK_CTRL_OFF);
-	val &= ~(LINK_CAPABLE_MASK | FAST_LINK_MODE);
-	meson_elb_writel(mp, val, PCIE_PORT_LINK_CTRL_OFF);
-
-	val = meson_elb_readl(mp, PCIE_PORT_LINK_CTRL_OFF);
-	val |= LINK_CAPABLE_X1;
-	meson_elb_writel(mp, val, PCIE_PORT_LINK_CTRL_OFF);
-
-	val = meson_elb_readl(mp, PCIE_GEN2_CTRL_OFF);
-	val &= ~NUM_OF_LANES_MASK;
-	meson_elb_writel(mp, val, PCIE_GEN2_CTRL_OFF);
-
-	val = meson_elb_readl(mp, PCIE_GEN2_CTRL_OFF);
-	val |= NUM_OF_LANES_X1 | DIRECT_SPEED_CHANGE;
-	meson_elb_writel(mp, val, PCIE_GEN2_CTRL_OFF);
-
 	meson_elb_writel(mp, 0x0, PCIE_BASE_ADDR0);
 	meson_elb_writel(mp, 0x0, PCIE_BASE_ADDR1);
 }
@@ -513,6 +485,7 @@  static int meson_pcie_probe(struct platform_device *pdev)
 	pci = &mp->pci;
 	pci->dev = dev;
 	pci->ops = &dw_pcie_ops;
+	pci->num_lanes = 1;
 
 	mp->phy = devm_phy_get(dev, "pcie");
 	if (IS_ERR(mp->phy)) {