From patchwork Thu Jul 15 06:51:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 477404 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp1408958jao; Wed, 14 Jul 2021 23:52:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxiEkDJi/1FvlREOCxbUrdsY8NkQKFnxvwHGrXg9PXAdvRQpG67L1DtinadqZtoq4RRqKF7 X-Received: by 2002:aa7:c2c4:: with SMTP id m4mr4626998edp.173.1626331978736; Wed, 14 Jul 2021 23:52:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626331978; cv=none; d=google.com; s=arc-20160816; b=EG4Ma74tSYFcLPs5nu0rldu3FkWcV54GG+72w/OvBuBm4x1Wc4ekoFu6Ag0US6hw6G n84TxPW/CAZo856a1CTgHiP6WxBvKvUPDUadWZAOmM3tkMu8LwsjMcrTPc0gsKoWCNRD GDDRTYMr/dp1s5hBpZ66wWrrQMNQTYUI8thy23jYQZgaC7bpslTSxCCBF/NHLj9JPfKK att04ReWn9DShjIvgjcVPpSRX+dN6ZLBrgzP+XCKdcWZBMrNfa8khjWy99rSeuFjwxWd c8CCxJ435NDb11iMl4DcGxQgBaoyyVGZdyxW0wulHm7/xVsAH7jpeN11AHx0PZpFyTxl 4yvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Wk7HbLkv/vIANHqNNOEh4RDAHHCmbdAxUcOGYwtm9R0=; b=o+znUwWoYka6AtwW8svjqJl4lArIBgO1cXpZqNMoj8+UmcwHcKYA+S/uqcjAuCmAU2 IJfaICe/NmyYZ+yyXaDF/BB5vTqnCzpgTOHXAYMrkPuzipnYuVO3+098CgCZKzIwQXP3 yO9r0j2HmUPZ8PWYzBB7zwe63QNR/k6pcNE5MW/IeL8Vv3KK32Ez1RaOyTbFpOQiQPSw 9g8aUAHZxqYB7uIoAbcUPra1EPFBrczi9e/DgMGxaSEaH8ZppqwRUWvvY7YFOc6cCBWj gC3EfpLtwVEQMgZj9XbT/QqQ3jciVChQmgxKTFgNLl1G5/Dnm6MGV1FbGnSlIr5U0UfQ 8hvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=OFD2XTj1; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id hd12si5850879ejc.121.2021.07.14.23.52.57; Wed, 14 Jul 2021 23:52:58 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=OFD2XTj1; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232564AbhGOGzs (ORCPT + 17 others); Thu, 15 Jul 2021 02:55:48 -0400 Received: from mail.kernel.org ([198.145.29.99]:58156 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234567AbhGOGzs (ORCPT ); Thu, 15 Jul 2021 02:55:48 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 89BFB61370; Thu, 15 Jul 2021 06:52:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1626331975; bh=LFdupZIcAp4gzbWBj3acmeg8NOUOs8LePDCjoa/EMXk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OFD2XTj1egWiuRNuV2gwRwZBJzoBEv0z4exH08tn2m6PqOCHorTmXwDpdpv3zThzg Zi9GNOtv5ARkmTx6IVxJaJeqUw1S1I4tKU+CuatbYDW9B9XGV4DUrx8ZU95Vd7m0Yd 4LTsIataqHlFccKu2Tjio2B3C4ELM1PUA8ZdkBKU1sr6f1iZYj4YN/0irHAUC1TpEn SD738U2FMDiDFHeNU+CDT/cn4cb3Uxvy99E8bpSq9dTOIhjz2Zi0DTjDCNDaViFKxm dkDvnd4bRT5GyiAf1s/wL+OipE6XuiOILaynyZPLrImzCreTTTg8RI//gMxVxpt9Xd 0d9doeRgN6M0g== From: Vinod Koul To: Rob Clark Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , David Airlie , Daniel Vetter , Jonathan Marek , Dmitry Baryshkov , Abhinav Kumar , Jeffrey Hugo , Sumit Semwal , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 06/11] drm/msm/disp/dpu1: Add DSC support in hw_ctl Date: Thu, 15 Jul 2021 12:21:58 +0530 Message-Id: <20210715065203.709914-7-vkoul@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210715065203.709914-1-vkoul@kernel.org> References: <20210715065203.709914-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Later gens of hardware have DSC bits moved to hw_ctl, so configure these bits so that DSC would work there as well Signed-off-by: Vinod Koul --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.31.1 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 2d4645e01ebf..aeea6add61ee 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -25,6 +25,8 @@ #define CTL_MERGE_3D_ACTIVE 0x0E4 #define CTL_INTF_ACTIVE 0x0F4 #define CTL_MERGE_3D_FLUSH 0x100 +#define CTL_DSC_ACTIVE 0x0E8 +#define CTL_DSC_FLUSH 0x104 #define CTL_INTF_FLUSH 0x110 #define CTL_INTF_MASTER 0x134 #define CTL_FETCH_PIPE_ACTIVE 0x0FC @@ -34,6 +36,7 @@ #define DPU_REG_RESET_TIMEOUT_US 2000 #define MERGE_3D_IDX 23 +#define DSC_IDX 22 #define INTF_IDX 31 #define CTL_INVALID_BIT 0xffff @@ -120,6 +123,7 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx) static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) { + DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, BIT(0) | BIT(1) | BIT(2) | BIT(3)); if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX)) DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH, @@ -128,7 +132,7 @@ static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) DPU_REG_WRITE(&ctx->hw, CTL_INTF_FLUSH, ctx->pending_intf_flush_mask); - DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask); + DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask | BIT(DSC_IDX)); } static inline void dpu_hw_ctl_trigger_flush(struct dpu_hw_ctl *ctx) @@ -507,6 +511,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, if (cfg->merge_3d) DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, BIT(cfg->merge_3d - MERGE_3D_0)); + DPU_REG_WRITE(c, CTL_DSC_ACTIVE, BIT(0) | BIT(1) | BIT(2) | BIT(3)); } static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,