Message ID | 20211202141726.1796793-10-dmitry.baryshkov@linaro.org |
---|---|
State | Superseded |
Headers | show |
Series | qcom: add support for PCIe0 on SM8450 platform | expand |
diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 8520911d6b7d..30ebafe9c6d2 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -346,10 +346,20 @@ vreg_l3h_0p91: ldo3 { }; }; +&pcie0_phy { + status = "okay"; + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; +}; + &qupv3_id_0 { status = "okay"; }; +&qupv3_id_1 { + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <28 4>, <36 4>; };
Enable PCIe0 PHY on the SM8450 QRD device. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 10 ++++++++++ 1 file changed, 10 insertions(+)