From patchwork Thu Dec 2 14:17:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 519844 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF09FC433EF for ; Thu, 2 Dec 2021 14:18:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358554AbhLBOVj (ORCPT ); Thu, 2 Dec 2021 09:21:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358480AbhLBOV0 (ORCPT ); Thu, 2 Dec 2021 09:21:26 -0500 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 52E27C06179C for ; Thu, 2 Dec 2021 06:17:41 -0800 (PST) Received: by mail-lf1-x132.google.com with SMTP id f18so71865684lfv.6 for ; Thu, 02 Dec 2021 06:17:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=43RnM0EBZFtZGvaWA+sQCGWkjNbH4H4Tyg6kxgcaORQ=; b=ejGl9PXt1HLmwDPLpJVfkY07WmTphpmQwtlNn8IQSX8Ru7zcf8HIAurlvCGom1oS+D 9E8GZwxp+fAgdNLK6/vvK4W6+ItzrjnR2f+JDO0knwVlpZXSHLUMs0D2dMx1+qvtgfio w8Yw5L6Bmxc6KuspHhJ60FatbVruiFczw2djf0/Res+QoqDBNnORuZ6QTRqsok6Fqmi8 6w1Re8OY7+TCGiJknZ1N88gjfdgwc1aYCly3xPu3VwtyQsqAWZKj1yGZTVBVPATXldu0 jm2U3WvRXiES4sbi9cfoy1zEjpJQs8XCHIdpKLQ4aA3XRI9A4XFEbCTwCqCwIV34Z+Iq qkJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=43RnM0EBZFtZGvaWA+sQCGWkjNbH4H4Tyg6kxgcaORQ=; b=Oyb4Fnzg3J23q9d9uyJr+4gj8GvhZJx6YbODlt/wmPlWsb9+ptyryxi5EGwl3LgrUH B2Sfr20Q63esBED7+iYs+DWK1kgqsl5t8jKaLoEr7xLfop4EJYUpacGbW9J71uFUoVne 2W+qdnN/bhMfOA8CNKsTp5ClMdNQ16Ti7E+/tvBLfVo4TaiVKNFZiTp2KMGkglfhYjsm UjJl50kYJDTYPi4eFmHiBWwnMSRQXkuwJ3Y8mBfdQcEqT8bG10urN6I3/SUZjqWGRpe0 YCzk3G6M+uUiyO6X0G8v/2A63k7pAuo6hTXy0knU3QQvkbEbXWP7ic1k9VBI2ktLdqu2 bYQA== X-Gm-Message-State: AOAM531zwZpfot+nANJxmVEaDjOXO16PWKb8DVS2OmG6aL8IiHNuXScW +U+Dl3FOKOGgshX0sSsTd0AtqA== X-Google-Smtp-Source: ABdhPJy7vyBxLfB88TWhp5juSAum1sDtJPBO1F/39GajvgVG1MKAyAwkal3eBblfyU5A+fKP2Z4Zzw== X-Received: by 2002:a05:6512:1510:: with SMTP id bq16mr11682896lfb.628.1638454659643; Thu, 02 Dec 2021 06:17:39 -0800 (PST) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id m15sm362487lfg.165.2021.12.02.06.17.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Dec 2021 06:17:39 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Vinod Koul , Kishon Vijay Abraham I , Stanimir Varbanov , Lorenzo Pieralisi Cc: Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v1 08/10] arm64: dts: qcom: sm8450: add PCIe0 root device Date: Thu, 2 Dec 2021 17:17:24 +0300 Message-Id: <20211202141726.1796793-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211202141726.1796793-1-dmitry.baryshkov@linaro.org> References: <20211202141726.1796793-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add device tree node for the first PCIe host found on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 101 +++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 4e825291839a..1cfdee1c38b6 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -583,6 +583,84 @@ uart7: serial@99c000 { }; }; + pcie0: pci@1c00000 { + compatible = "qcom,pcie-sm8450"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, + <&pcie0_lane>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; + clock-names = "pipe", + "pipe_mux", + "phy_pipe", + "ref", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "aggre0", + "aggre1"; + + iommus = <&apps_smmu 0x1c00 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_0_GDSC>; + power-domain-names = "gdsc"; + + phys = <&pcie0_lane>; + phy-names = "pciephy"; + + perst-gpio = <&tlmm 94 GPIO_ACTIVE_LOW>; + enable-gpio = <&tlmm 96 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + + interconnects = <&pcie_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; + interconnect-names = "pci"; + + status = "disabled"; + }; + pcie0_phy: phy@1c06000 { compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; reg = <0 0x01c06000 0 0x200>; @@ -717,6 +795,29 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 211>; wakeup-parent = <&pdc>; + pcie0_default_state: pcie0-default { + perst { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio95"; + function = "pcie0_clkreqn"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio96"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + qup_uart7_default_state: qup-uart3-default-state { rx { pins = "gpio26";