From patchwork Mon May 30 08:08:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 577304 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 045F0C433FE for ; Mon, 30 May 2022 08:09:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232539AbiE3IJB (ORCPT ); Mon, 30 May 2022 04:09:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232527AbiE3IJA (ORCPT ); Mon, 30 May 2022 04:09:00 -0400 Received: from mail-pf1-x431.google.com (mail-pf1-x431.google.com [IPv6:2607:f8b0:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F86375205 for ; Mon, 30 May 2022 01:08:57 -0700 (PDT) Received: by mail-pf1-x431.google.com with SMTP id j6so9919637pfe.13 for ; Mon, 30 May 2022 01:08:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Vz2goCu8HSSqj1z/SCgL7p1ZSvFJFBtaYvPt923/tkk=; b=HjUaNLgpj+1HCHz8WV11s5EFrLkt8jZwObVlRBh41LOTSV5vYht3tzqCBeDYQvSzY1 DtzRSz3npLFzeZ7N+1LdcQT90juikktl1Zej+IsJFJdlsU2LVfc/UHCw2QXeTF36cjv6 W2UUNwvXlDuFihHZBfHmKAzyVw96nTwQlOsJbS7TNkzP27sZkzup2gF7jg0bXXaHYhhE S1Fjmkn05XwCez20Mb8gSCi0HL3RN4MCpF4BNmZPCSxOlUvqzHTzjrJmHTo3CFgcnftw 6gY0NoFBEpweEQ6aDWPGGArq+iYIHdy56VvXzuoV034IsADCamYFgRWLaQktq6KERWjS SQxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Vz2goCu8HSSqj1z/SCgL7p1ZSvFJFBtaYvPt923/tkk=; b=XwTrvA6I8ts1Ww250XmEMvGOXupDPDzXl5dVbcEVoMmfeLZ/6Q8joj87NzYytYXmj1 UkICwA9Y008+Og3bJIiLw8sjEWx+1K6F1XAmkvgvllWug7o03gEhmH8xc0faDnMj6OmR 43D83LoiMug16bO6BsW5h2XJaxvWh6haH4RX9bN0Y7wogTVNsnzQZrcaQ1WtO0mPXnMe zYK/pI+Bwg7kHwJi3ZhNGv454ULxu5FjSMAoPoONzznqeWLbXh4chu+RR2N0f+VtyDGP benx9ek61Op91Vk+G7jL0IZU/GxLUIArrG1EPrefTjSQupoRhOVC3PJHja8cAHEW8rOO /NMQ== X-Gm-Message-State: AOAM532sMDomjqjvydKa/iN4Qa3J/GmZK8mGp5TIoC42ZUOCjeYt7mSy noto9gd7Y5+39CuaRRjQavDd X-Google-Smtp-Source: ABdhPJyTSnLbwM3Yh43BnEZETXGDd6hYwOc4zYHkTWy+pn7V/vLULqcqYsLgxrBMtuxPwHrXNchj1A== X-Received: by 2002:a63:f156:0:b0:3ab:ada6:b463 with SMTP id o22-20020a63f156000000b003abada6b463mr46583877pgk.462.1653898136828; Mon, 30 May 2022 01:08:56 -0700 (PDT) Received: from localhost.localdomain ([220.158.159.114]) by smtp.gmail.com with ESMTPSA id io17-20020a17090312d100b0015e8d4eb285sm8450345plb.207.2022.05.30.01.08.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 May 2022 01:08:56 -0700 (PDT) From: Manivannan Sadhasivam To: tglx@linutronix.de, maz@kernel.org, bjorn.andersson@linaro.org Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 1/3] ARM: dts: qcom: sdx55: Fix the IRQ trigger type for UART Date: Mon, 30 May 2022 13:38:40 +0530 Message-Id: <20220530080842.37024-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220530080842.37024-1-manivannan.sadhasivam@linaro.org> References: <20220530080842.37024-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The trigger type should be LEVEL_HIGH. So fix it! Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index d455795da44c..b75e672c239d 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -206,7 +206,7 @@ gcc: clock-controller@100000 { blsp1_uart3: serial@831000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x00831000 0x200>; - interrupts = ; + interrupts = ; clocks = <&gcc 30>, <&gcc 9>; clock-names = "core", "iface";