Message ID | 20220818220628.339366-9-robimarko@gmail.com |
---|---|
State | Accepted |
Commit | fe6d5b8de04780e7ec27037b836324b59fade45b |
Headers | show |
Series | [v3,1/9] clk: qcom: clk-rcg2: add rcg2 mux ops | expand |
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 5b62d7590fc6..bace14b742a1 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -709,6 +709,14 @@ apcs_glb: mailbox@b111000 { #mbox-cells = <1>; }; + a53pll: clock@b116000 { + compatible = "qcom,ipq8074-a53pll"; + reg = <0x0b116000 0x40>; + #clock-cells = <0>; + clocks = <&xo>; + clock-names = "xo"; + }; + timer@b120000 { #address-cells = <1>; #size-cells = <1>;
Add the required node for A53 PLL which will be used to provide the CPU clock via APCS for APSS scaling. Signed-off-by: Robert Marko <robimarko@gmail.com> --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)