From patchwork Sat Oct 1 03:06:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melody Olvera X-Patchwork-Id: 611449 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26E85C433FE for ; Sat, 1 Oct 2022 03:09:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232930AbiJADJJ (ORCPT ); Fri, 30 Sep 2022 23:09:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231854AbiJADHq (ORCPT ); Fri, 30 Sep 2022 23:07:46 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D290B98A78; Fri, 30 Sep 2022 20:07:16 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2912uJSm004685; Sat, 1 Oct 2022 03:07:14 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=hFnUFuEMF5I0mO528pZxcMDQLBDaselO4QfZjPs0xds=; b=cCrUdczWYX5vb/+WLNrX5y9P9+xTE1NKi/wMfcn4jAWaD5B26z55fcXlLUAqP4j+tkEb 078tgiSlCFE5uixMmJ2ggIlxxkw1tOusNcRhTKIUZxZ20i8qJAHaz7/VmExhQop9Y2ly EgTfv5hNsSd1sh4NXqpuT/4AMT6YVVoyWPhLJHbjiRF5fMbKUT7zxwK4WVE13tPf3ta/ QTMu84EzZacp5sLP0nHofuiJCewi97B9OjU3IZU9/MYj2gpLxVKa71hXokGwWUwcE5o2 uhDK/BGWPwglDS9Rs1sxYpbpJVW9PtPfT8f4lqXD3P8Xy4wmTU+OvY0SoDpPo+dai/dm yg== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3jx6by8tws-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 01 Oct 2022 03:07:13 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29137DH9009833 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 1 Oct 2022 03:07:13 GMT Received: from hu-molvera-sd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 30 Sep 2022 20:07:12 -0700 From: Melody Olvera To: Andy Gross , Bjorn Andersson , Rob Herring , "Krzysztof Kozlowski" CC: , , , Melody Olvera Subject: [PATCH 03/19] arm64: dts: qcom: qdru1000: Add tlmm nodes Date: Fri, 30 Sep 2022 20:06:40 -0700 Message-ID: <20221001030656.29365-4-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221001030656.29365-1-quic_molvera@quicinc.com> References: <20221001030656.29365-1-quic_molvera@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 17URZsvXSK8cBqRqnA9EHj9gNI-Ri6WI X-Proofpoint-ORIG-GUID: 17URZsvXSK8cBqRqnA9EHj9gNI-Ri6WI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-01_02,2022-09-29_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=716 bulkscore=0 spamscore=0 phishscore=0 mlxscore=0 suspectscore=0 impostorscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210010016 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add tlmm node for the QDU1000 and QRU1000 SoCs and the uart pin configuration. Signed-off-by: Melody Olvera --- arch/arm64/boot/dts/qcom/qdru1000.dtsi | 30 ++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi index 3610f94bef35..39b9a00d3ad8 100644 --- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi @@ -235,6 +235,8 @@ uart7: serial@99c000 { reg = <0x0 0x99c000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart7_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -248,6 +250,34 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + tlmm: pinctrl@f000000 { + compatible = "qcom,qdu1000-tlmm", "qcom,qru1000-tlmm"; + reg = <0x0 0xf000000 0x0 0x1000000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 151>; + wakeup-parent = <&pdc>; + + qup_uart7_default: qup-uart7-default { + tx { + pins = "gpio134"; + function = "qup0_se7_l2"; + drive-strength = <2>; + bias-disable; + }; + + rx { + pins = "gpio135"; + function = "qup0_se7_l3"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,pdc"; reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;