From patchwork Fri Nov 11 13:55:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 625767 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71A51C433FE for ; Fri, 11 Nov 2022 13:59:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234143AbiKKN7Q (ORCPT ); Fri, 11 Nov 2022 08:59:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234109AbiKKN6v (ORCPT ); Fri, 11 Nov 2022 08:58:51 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 18057742D2; Fri, 11 Nov 2022 05:55:42 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id E2ED96602A5A; Fri, 11 Nov 2022 13:55:39 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1668174940; bh=XDujAn0ZeYKReEqH3WwrDRbPR8DoO7W2378dAKf4P6w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hzM22CMbpHIYs4+DUMrnQ2LGSeIGTK0W+D2Ep4UKA6F4EXRzhmnSSl31+Rqrn/AcC zaDhrcOdFuVXMW22Sa9JLsa3joMbb40EZjv19EC0JtZL1LD6XaJBINI8UM3JCrEAz4 +Sgz8gc01CRJNrUFxGgPO/2RhOhco0EaRjMKq+mmqSlQr/ymrvS6e4uUC+1i6IWGsf 0QIL/7MtTufaARaEameRpY/daftaQvodSUMLDtQL7KFoLNsAwDRF7vkIdlNtHvJvhe SbMKsWizdNtGIekU5ue/0P1RqAW9V7J8YQJvrPA6hmVHuHriWU/AM1BdyJ5ys+qv6D FsPY/ya6t96SQ== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@linaro.org, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, robdclark@gmail.com, linux-arm-msm@vger.kernel.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, marijn.suijten@somainline.org, kernel@collabora.com, luca@z3ntu.xyz, a39.skl@gmail.com, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno Subject: [PATCH 3/7] iommu/qcom: Properly reset the IOMMU context Date: Fri, 11 Nov 2022 14:55:21 +0100 Message-Id: <20221111135525.204134-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221111135525.204134-1-angelogioacchino.delregno@collabora.com> References: <20221111135525.204134-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Avoid context faults by resetting the context(s) entirely at detach_dev() time and also do the same before programming the context for domain initialization. Signed-off-by: AngeloGioacchino Del Regno --- drivers/iommu/arm/arm-smmu/qcom_iommu.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c index 491a8093f3d6..5b127ac41b5e 100644 --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c @@ -223,6 +223,20 @@ static irqreturn_t qcom_iommu_fault(int irq, void *dev) return IRQ_HANDLED; } +static void qcom_iommu_reset_ctx(struct qcom_iommu_ctx *ctx) +{ + iommu_writel(ctx, ARM_SMMU_CB_FAR, 0); + iommu_writel(ctx, ARM_SMMU_CB_FSR, 0); + iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR1, 0); + iommu_writel(ctx, ARM_SMMU_CB_PAR, 0); + iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0, 0); + iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0); + iommu_writel(ctx, ARM_SMMU_CB_TCR2, 0); + iommu_writel(ctx, ARM_SMMU_CB_TCR, 0); + iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, 0); + iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0); +} + static int qcom_iommu_init_domain(struct iommu_domain *domain, struct qcom_iommu_dev *qcom_iommu, struct device *dev) @@ -273,6 +287,8 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, ctx->secure_init = true; } + qcom_iommu_reset_ctx(ctx); + /* TTBRs */ iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, pgtbl_cfg.arm_lpae_s1_cfg.ttbr | @@ -401,8 +417,8 @@ static void qcom_iommu_detach_dev(struct iommu_domain *domain, struct device *de for (i = 0; i < fwspec->num_ids; i++) { struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); - /* Disable the context bank: */ - iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0); + /* Disable and reset the context bank */ + qcom_iommu_reset_ctx(ctx); ctx->domain = NULL; }