From patchwork Wed Jan 18 16:25:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 643733 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29300C38159 for ; Wed, 18 Jan 2023 16:27:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229820AbjARQ1o (ORCPT ); Wed, 18 Jan 2023 11:27:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229581AbjARQ1Y (ORCPT ); Wed, 18 Jan 2023 11:27:24 -0500 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9A3C58989 for ; Wed, 18 Jan 2023 08:25:17 -0800 (PST) Received: by mail-wm1-x332.google.com with SMTP id k22-20020a05600c1c9600b003d1ee3a6289so1947114wms.2 for ; Wed, 18 Jan 2023 08:25:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=hOclNqxJMc8W6WVvj69yNcLJ2v6PJKY1XvpbHS40Uoc=; b=J+NGYLKnSMXV0uu+voTTOnKvSUS2Xu9T7P7XMzpynszBuYRnlUzjkmmlSdfgY0TGZ+ XvhAZzPRbZdy0NelQ4vFO9AfFGQMjJHuVQQdyFk4uYXF6eEfffa7Ux81qWFpaZ0WF89c P9aooZrELFbH+Uum/qZ3fNRFtDYUqqBMFMbUO5VmNYSXRyTv0aWH5VLrAuMaC0gl0ytC 8zdFK1H9PUnpXPtfaWDACkgMh7VGDVzIUR2WzpLJhcsXDmrrjxUwxc1lKKDFm5icSxVY ur5W0fl/GnhWoJukRE4fqs74czalfw6P6AX5Au7nil2LrsK/8JJF4foSN8osKad0PQjk fVOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hOclNqxJMc8W6WVvj69yNcLJ2v6PJKY1XvpbHS40Uoc=; b=QlwRLpp6abvBcFPa3mHeGIHEOCkmKbm6Bs2ECvD1Q7NskHX3w01gqAjpIc4jO+mOCf EC3HxRjFrRMNXOxXJdzgbj0o7ZnTgvPplmLO7K+K3erjXcvnvRwAXLRafpQ6HYCjMU0D ZCE76wU3Q6Me4QrnQV/szymwVg3SGiPUELh546MtGzwgq4y9+v3+8xcIsT9TwMP6Gxsp 8TfJPbV2MLMapJGWfUvi0hBmty5wMgZlOCvOO4FMkLZ7+X2WWhV9+2YW9wO4s0ZX9o0T jt91hGcC5OKoLmpWJ6R73L4gmp0RhtIW4xVeCtAWDlSqQtFw1nJjKC5fo0f399HiFeFm AGPQ== X-Gm-Message-State: AFqh2kpU6XiYvrCWrW4EVTuxHfmFP3wpDKFLe6WH+xlgY2gxLSMc6pqh /5jE3hhAt1tcPp96YbgyKZDNRCRhoxF8kANWJCc= X-Google-Smtp-Source: AMrXdXvmj22Zxf0lZKm4g1KxXaki1k4xObaQ5mto5eodq82swJxk7kuTHaoPJQMJkXipOj1vMw62sg== X-Received: by 2002:a05:600c:2116:b0:3d6:10e:68a8 with SMTP id u22-20020a05600c211600b003d6010e68a8mr3328857wml.0.1674059116508; Wed, 18 Jan 2023 08:25:16 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id m27-20020a05600c3b1b00b003db012d49b7sm3670695wms.2.2023.01.18.08.25.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 08:25:16 -0800 (PST) From: Neil Armstrong Date: Wed, 18 Jan 2023 17:25:12 +0100 Subject: [PATCH v3 2/3] arm64: dts: qcom: sm8550: add adsp, cdsp & mdss nodes MIME-Version: 1.0 Message-Id: <20221115-topic-sm8550-upstream-dts-remoteproc-v3-2-815a1753de34@linaro.org> References: <20221115-topic-sm8550-upstream-dts-remoteproc-v3-0-815a1753de34@linaro.org> In-Reply-To: <20221115-topic-sm8550-upstream-dts-remoteproc-v3-0-815a1753de34@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This adds support for the aDSP, cDSP and MPSS Subsystems found in the SM8550 SoC. The aDSP, cDSP and MPSS needs: - smp2p nodes to get event back from the subsystems - remoteproc nodes with glink-edge subnodes providing all needed resources to start and run the subsystems In addition, the MPSS Subsystem needs a rmtfs_mem dedicated memory zone. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 337 +++++++++++++++++++++++++++++++++++ 1 file changed, 337 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index ee3e5150a976..bfdb10e00141 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -541,6 +541,15 @@ adspslpi_mem: adspslpi-region@9ea00000 { /* Linux kernel image is loaded at 0xa8000000 */ + rmtfs_mem: rmtfs-region@d4a80000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0xd4a80000 0x0 0x280000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + mpss_dsm_mem: mpss-dsm-region@d4d00000 { reg = <0 0xd4d00000 0 0x3300000>; no-map; @@ -632,6 +641,89 @@ hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { }; }; + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + smp2p_modem_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_modem_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { compatible = "simple-bus"; ranges = <0 0 0 0 0x10 0>; @@ -1653,6 +1745,48 @@ tcsr: clock-controller@1fc0000 { #reset-cells = <1>; }; + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,sm8550-mpss-pas"; + reg = <0x0 0x04080000 0x0 0x4040>; + + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM8550_CX>, + <&rpmhpd SM8550_MSS>; + power-domain-names = "cx", "mss"; + + interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; + + memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_modem_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + label = "mpss"; + qcom,remote-pid = <1>; + }; + }; + lpass_lpiaon_noc: interconnect@7400000 { compatible = "qcom,sm8550-lpass-lpiaon-noc"; reg = <0 0x07400000 0 0x19080>; @@ -2700,12 +2834,215 @@ system-cache-controller@25000000 { interrupts = ; }; + remoteproc_adsp: remoteproc@30000000 { + compatible = "qcom,sm8550-adsp-pas"; + reg = <0x0 0x30000000 0x0 0x100>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM8550_LCX>, + <&rpmhpd SM8550_LMX>; + power-domain-names = "lcx", "lmx"; + + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; + + memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1003 0x80>, + <&apps_smmu 0x1063 0x0>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1004 0x80>, + <&apps_smmu 0x1064 0x0>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1005 0x80>, + <&apps_smmu 0x1065 0x0>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1006 0x80>, + <&apps_smmu 0x1066 0x0>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1007 0x80>, + <&apps_smmu 0x1067 0x0>; + }; + }; + }; + }; + nsp_noc: interconnect@320c0000 { compatible = "qcom,sm8550-nsp-noc"; reg = <0 0x320c0000 0 0xe080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; + + remoteproc_cdsp: remoteproc@32300000 { + compatible = "qcom,sm8550-cdsp-pas"; + reg = <0x0 0x32300000 0x0 0x1400000>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM8550_CX>, + <&rpmhpd SM8550_MXC>, + <&rpmhpd SM8550_NSP>; + power-domain-names = "cx", "mxc", "nsp"; + + interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; + + memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_cdsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "cdsp"; + qcom,remote-pid = <5>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + #address-cells = <1>; + #size-cells = <0>; + + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x1961 0x0>, + <&apps_smmu 0x0c01 0x20>, + <&apps_smmu 0x19c1 0x10>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x1962 0x0>, + <&apps_smmu 0x0c02 0x20>, + <&apps_smmu 0x19c2 0x10>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1963 0x0>, + <&apps_smmu 0x0c03 0x20>, + <&apps_smmu 0x19c3 0x10>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1964 0x0>, + <&apps_smmu 0x0c04 0x20>, + <&apps_smmu 0x19c4 0x10>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1965 0x0>, + <&apps_smmu 0x0c05 0x20>, + <&apps_smmu 0x19c5 0x10>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1966 0x0>, + <&apps_smmu 0x0c06 0x20>, + <&apps_smmu 0x19c6 0x10>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1967 0x0>, + <&apps_smmu 0x0c07 0x20>, + <&apps_smmu 0x19c7 0x10>; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x1968 0x0>, + <&apps_smmu 0x0c08 0x20>, + <&apps_smmu 0x19c8 0x10>; + }; + + /* note: secure cb9 in downstream */ + }; + }; + }; }; thermal-zones {