Message ID | 20221116214841.1116735-1-robimarko@gmail.com |
---|---|
State | Superseded |
Headers | show |
Series | [1/9] arm64: dts: qcom: ipq8074: fix Gen2 PCIe QMP PHY | expand |
On 16/11/2022 22:48, Robert Marko wrote: > Sort the compatibles list alphabetically for maintenance. > > Signed-off-by: Robert Marko <robimarko@gmail.com> > --- > Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 8 ++++---- Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On 16/11/2022 22:48, Robert Marko wrote: > IPQ8074 has one Gen2 and one Gen3 PCIe port, with Gen2 already supported. > Document Gen3 port which uses the same controller as IPQ6018. > > Signed-off-by: Robert Marko <robimarko@gmail.com> > --- Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 4b4cd3eaf6c8..6649a758d8df 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -277,9 +277,9 @@ pcie_qmp1: phy@8e000 { status = "disabled"; pcie_phy1: phy@8e200 { - reg = <0x8e200 0x16c>, + reg = <0x8e200 0x130>, <0x8e400 0x200>, - <0x8e800 0x4f4>; + <0x8e800 0x1f8>; #phy-cells = <0>; #clock-cells = <0>; clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
Serdes register space sizes are incorrect, update them to match the actual sizes from downstream QCA 5.4 kernel. Fixes: 942bcd33ed45 ("arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes") Signed-off-by: Robert Marko <robimarko@gmail.com> --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)