| Message ID | 20221129204616.47006-4-a39.skl@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | SM6115 DTS changes | expand |
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 0340ed21be05..2003a2519a54 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -842,6 +842,17 @@ intc: interrupt-controller@f200000 { redistributor-stride = <0x0 0x20000>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; + + cpufreq_hw: cpufreq@f521000 { + compatible = "qcom,cpufreq-hw"; + reg = <0x0f521000 0x1000>, <0x0f523000 0x1000>; + + reg-names = "freq-domain0", "freq-domain1"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; }; timer {
Add cpufreq-hw node and assign qcom,freq-domain properties to CPUs to enable CPU clock scaling. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+)