[v3,05/19] PCI: qcom: Use lower case for hex

Message ID	20230310040816.22094-6-manivannan.sadhasivam@linaro.org
State	Superseded
Headers	show Return-Path: <linux-arm-msm-owner@vger.kernel.org> From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Subject: [PATCH v3 05/19] PCI: qcom: Use lower case for hex Date: Fri, 10 Mar 2023 09:38:02 +0530 Message-Id: <20230310040816.22094-6-manivannan.sadhasivam@linaro.org> In-Reply-To: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> References: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Qcom PCIe cleanups and improvements \| expand [v3,00/19] Qcom PCIe cleanups and improvements [v3,01/19] PCI: qcom: Remove PCIE20_ prefix from register definitions [v3,02/19] PCI: qcom: Sort and group registers and bitfield definitions [v3,03/19] PCI: qcom: Use bitfield definitions for register fields [v3,04/19] PCI: qcom: Add missing macros for register fields [v3,05/19] PCI: qcom: Use lower case for hex [v3,06/19] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.1.0 [v3,07/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 1.0.0 [v3,08/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.2 [v3,09/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.3 [v3,10/19] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.3.3 [v3,11/19] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.4.0 [v3,12/19] PCI: qcom: Use macros for defining total no. of clocks & supplies [v3,13/19] PCI: qcom: Rename qcom_pcie_config_sid_sm8250() to reflect IP version [v3,14/19] dt-bindings: PCI: qcom: Add "mhi" register region to supported SoCs [v3,15/19] arm64: dts: qcom: sdm845: Add "mhi" region to the PCIe nodes [v3,16/19] arm64: dts: qcom: sm8250: Add "mhi" region to the PCIe nodes [v3,17/19] arm64: dts: qcom: sc8280xp: Add "mhi" region to the PCIe nodes [v3,18/19] PCI: qcom: Expose link transition counts via debugfs for v1.9.0 & v2.7.0 [v3,19/19] PCI: qcom: Expose link transition counts via debugfs for v2.4.0

Message ID

20230310040816.22094-6-manivannan.sadhasivam@linaro.org

State

Superseded

Headers

From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com,
        krzysztof.kozlowski+dt@linaro.org, robh@kernel.org
Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org,
        devicetree@vger.kernel.org, linux-pci@vger.kernel.org,
        linux-kernel@vger.kernel.org, quic_srichara@quicinc.com,
        Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH v3 05/19] PCI: qcom: Use lower case for hex
Date: Fri, 10 Mar 2023 09:38:02 +0530
Message-Id: <20230310040816.22094-6-manivannan.sadhasivam@linaro.org>
In-Reply-To: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org>
References: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

Series

Qcom PCIe cleanups and improvements | expand

Commit Message

Manivannan Sadhasivam March 10, 2023, 4:08 a.m. UTC

To maintain uniformity, let's use lower case for representing hexadecimal
numbers.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 926a531fda3a..4179ac973147 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -39,17 +39,17 @@ 
 #define PARF_PCS_DEEMPH				0x34
 #define PARF_PCS_SWING				0x38
 #define PARF_PHY_CTRL				0x40
-#define PARF_PHY_REFCLK				0x4C
+#define PARF_PHY_REFCLK				0x4c
 #define PARF_CONFIG_BITS			0x50
 #define PARF_DBI_BASE_ADDR			0x168
-#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16C /* Register offset specific to IP ver 2.3.3 */
+#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16c /* Register offset specific to IP ver 2.3.3 */
 #define PARF_MHI_CLOCK_RESET_CTRL		0x174
 #define PARF_AXI_MSTR_WR_ADDR_HALT		0x178
-#define PARF_AXI_MSTR_WR_ADDR_HALT_V2		0x1A8
-#define PARF_Q2A_FLUSH				0x1AC
-#define PARF_LTSSM				0x1B0
+#define PARF_AXI_MSTR_WR_ADDR_HALT_V2		0x1a8
+#define PARF_Q2A_FLUSH				0x1ac
+#define PARF_LTSSM				0x1b0
 #define PARF_SID_OFFSET				0x234
-#define PARF_BDF_TRANSLATE_CFG			0x24C
+#define PARF_BDF_TRANSLATE_CFG			0x24c
 #define PARF_SLV_ADDR_SPACE_SIZE		0x358
 #define PARF_DEVICE_TYPE			0x1000
 #define PARF_BDF_TO_SID_TABLE_N			0x2000
@@ -60,7 +60,7 @@ 
 /* DBI registers */
 #define AXI_MSTR_RESP_COMP_CTRL0		0x818
 #define AXI_MSTR_RESP_COMP_CTRL1		0x81c
-#define MISC_CONTROL_1_REG			0x8BC
+#define MISC_CONTROL_1_REG			0x8bc
 
 /* PARF_SYS_CTRL register fields */
 #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN	BIT(29)

[v3,05/19] PCI: qcom: Use lower case for hex

Commit Message

Patch