From patchwork Wed Apr 26 19:20:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhinav Kumar X-Patchwork-Id: 677149 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75AF4C7618E for ; Wed, 26 Apr 2023 19:21:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239458AbjDZTVB (ORCPT ); Wed, 26 Apr 2023 15:21:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232813AbjDZTU7 (ORCPT ); Wed, 26 Apr 2023 15:20:59 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B37DB188; Wed, 26 Apr 2023 12:20:58 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33QFutcF005107; Wed, 26 Apr 2023 19:20:50 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=ohCHxWuUVY7OO8meTKcLOoiLqkpM2lzEy7Qranv9Erk=; b=Lp4jkiV6+6KbiI8GXEpM0p1ohG4LwQKZIyM0rx5XmfjMc30zMNe4brwrZSTJQXhzIAMp NC5ci/A2oGMY6htK/B/4gw3OJUOQeXurKGBpbrYGXBF2Q0GKgO09oW1m1/k55xN6rV2z Wnu85pEuKpmtFtpbGZpC7uE4a5poXGWZ2FCUtcj+FxbgX6HkYMaSrtctrmlhYlOYBW6F 0E0PlBBjyFq0qQhO5fAHHvbwcdJVKSRwBb4xTAjXEYb8VudWvebAoUA+bH2EhS4vTgyr w2fnemRPF25ZlsCfMrpx0RxSCv5UeeTSrEgDjD+cejnju9ED8CIlvWIZzW0vpL/9U7Fv Pw== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3q6x62ht0m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Apr 2023 19:20:50 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 33QJKnS4020436 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Apr 2023 19:20:49 GMT Received: from abhinavk-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Wed, 26 Apr 2023 12:20:49 -0700 From: Abhinav Kumar To: , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter CC: , , , , Subject: [PATCH 2/4] drm/msm/dpu: remove DPU_DSPP_IGC handling in dspp flush Date: Wed, 26 Apr 2023 12:20:32 -0700 Message-ID: <20230426192035.5088-2-quic_abhinavk@quicinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230426192035.5088-1-quic_abhinavk@quicinc.com> References: <20230426192035.5088-1-quic_abhinavk@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: wtivMk240fwDD87RecvgWH_v3dF37err X-Proofpoint-ORIG-GUID: wtivMk240fwDD87RecvgWH_v3dF37err X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-26_10,2023-04-26_03,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 phishscore=0 spamscore=0 malwarescore=0 impostorscore=0 suspectscore=0 mlxscore=0 bulkscore=0 clxscore=1015 mlxlogscore=841 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304260172 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Inverse gamma correction blocks (IGC) are not used today so lets remove the usage of DPU_DSPP_IGC in the dspp flush to make it easier to remove IGC from the catalog. We can add this back when IGC is properly supported in DPU with one of the standard DRM properties. Signed-off-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 57adaebab563..b2a1f83ac72c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -330,9 +330,6 @@ static void dpu_hw_ctl_update_pending_flush_dspp_sub_blocks( return; switch (dspp_sub_blk) { - case DPU_DSPP_IGC: - ctx->pending_dspp_flush_mask[dspp - DSPP_0] |= BIT(2); - break; case DPU_DSPP_PCC: ctx->pending_dspp_flush_mask[dspp - DSPP_0] |= BIT(4); break;