From patchwork Thu Jul 27 14:45:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 707087 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DDC3C04A94 for ; Thu, 27 Jul 2023 14:46:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233980AbjG0Oq2 (ORCPT ); Thu, 27 Jul 2023 10:46:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234033AbjG0OqF (ORCPT ); Thu, 27 Jul 2023 10:46:05 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 346D33585 for ; Thu, 27 Jul 2023 07:45:51 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-4fbf09a9139so1829256e87.2 for ; Thu, 27 Jul 2023 07:45:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690469149; x=1691073949; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8bYdl5KO0mcXnWax9jXxtCfyWjeeAJPJsi/VIzVkVic=; b=itfDaqs7HG1PvaneA77u3yxpFVEjzr+x2nD+NNTolNZO4r6bTy8w1sRJnmh708/L2T llL1RNsyPmJcu3vfHJuvzpyjofXlfrAFMKww1+3EH2KSzq44GAWBkBUsDUx6A/toJ/SE +SIoFVc8PDafN1csvaD0lvhhqAM1QNhK3+5IHf5fbDl4jGkM1iFD4z3C41rV7cPrV5fs YKPlVGPBqG4s2kqEn3yvzmjf3oiXYa8/6dSwaiMjqSHqUS0O01S7M8h5trEKFYdS2buu /InT2Pf8RG8f6HdE+BW1+VSs0YEAXSd2tdRiX9mQgUZRyQsVjbacSatBuyhxdhpg3N4U PL1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690469149; x=1691073949; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8bYdl5KO0mcXnWax9jXxtCfyWjeeAJPJsi/VIzVkVic=; b=W066kJowxLFIUy0MxIASPEcIJjB7Ka21PwWpVvMvUqFqB09c210MAv+++sOLmOXNRA vXFC1Wht6YQM52bbYCMzrp0fP4RmBYjxXjmoWw+TdvaCtLv0IXXQpgT6Ij/Up884b2Cj FhVczcqS8nPkoX4+d1OJQ5bwFqySV+m0Sg75qvYTBGPTQ12+ONE0MZsyJdlAyJ2IAJmY lwSbTGWqm5jdiFXl/p/4pTIiqBfHxt3gEaTsdkrmxTV1W9oxLg8+17EAMZXMC0RoENZf BqawnfzwruIHC8V0yS16N3wpOXRFygdpT+Dv3ZFzTKd8xc/5/VOpOoqaelkEzoQ6s74F jLyA== X-Gm-Message-State: ABy/qLZmYOqbNfNhyUaCbSrTyT7BRTPbC8fVoJEh3vibdtJ/6sGUz+86 7D0nLVzF6Uu8PxjNgJiL4+PoxQ== X-Google-Smtp-Source: APBJJlFXEKX6qD4sbH0evYtdKpRyhUlBnu9uQ1+tvFs6f71CfsKWz0gpYrTqKLCPzzu2NculrvIDjw== X-Received: by 2002:a19:e612:0:b0:4f8:752f:3722 with SMTP id d18-20020a19e612000000b004f8752f3722mr1465424lfh.5.1690469149402; Thu, 27 Jul 2023 07:45:49 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id d28-20020ac2545c000000b004fb86662871sm334110lfn.233.2023.07.27.07.45.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 07:45:48 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Neil Armstrong Subject: [PATCH v4 5/5] drm/msm/dpu: drop compatibility INTR defines Date: Thu, 27 Jul 2023 17:45:43 +0300 Message-Id: <20230727144543.1483630-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230727144543.1483630-1-dmitry.baryshkov@linaro.org> References: <20230727144543.1483630-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org While reworking interrupts masks, it was easier to keep old MDP_INTFn_7xxx_INTR and MDP_INTFn_7xxx_TEAR_INTR symbols. Now it is time to drop them and use unified symbol names. Reviewed-by: Neil Armstrong Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 4 ++-- .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +- .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 4 ++-- .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 4 ++-- .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 13 ------------- 6 files changed, 9 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 90efde5e9da5..941b585bd56f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -329,7 +329,7 @@ static const struct dpu_intf_cfg sm8350_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), }, { .name = "intf_2", .id = INTF_2, .base = 0x36000, .len = 0x2c4, @@ -339,7 +339,7 @@ static const struct dpu_intf_cfg sm8350_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), }, { .name = "intf_3", .id = INTF_3, .base = 0x37000, .len = 0x280, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 0a5dcec343fc..b18bb7ce2f94 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -210,7 +210,7 @@ static const struct dpu_intf_cfg sc7280_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), }, { .name = "intf_5", .id = INTF_5, .base = 0x39000, .len = 0x280, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 7b1395f9e710..b08096f0d50b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -344,7 +344,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), }, { .name = "intf_2", .id = INTF_2, .base = 0x36000, .len = 0x300, @@ -354,7 +354,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), }, { .name = "intf_3", .id = INTF_3, .base = 0x37000, .len = 0x280, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 4999f3d8f2e2..9e0ad71c12a8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -352,7 +352,7 @@ static const struct dpu_intf_cfg sm8450_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), }, { .name = "intf_2", .id = INTF_2, .base = 0x36000, .len = 0x300, @@ -362,7 +362,7 @@ static const struct dpu_intf_cfg sm8450_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), }, { .name = "intf_3", .id = INTF_3, .base = 0x37000, .len = 0x280, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 401c6c2da367..2a19e4c0af1a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -366,7 +366,7 @@ static const struct dpu_intf_cfg sm8550_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), }, { .name = "intf_2", .id = INTF_2, .base = 0x36000, .len = 0x300, @@ -376,7 +376,7 @@ static const struct dpu_intf_cfg sm8550_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), }, { .name = "intf_3", .id = INTF_3, .base = 0x37000, .len = 0x280, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h index 6e0d0188edc6..dab761e54863 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h @@ -36,19 +36,6 @@ enum dpu_hw_intr_reg { #define MDP_INTFn_INTR(intf) (MDP_INTF0_INTR + (intf - INTF_0)) -/* compatibility */ -#define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR -#define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR -#define MDP_INTF2_7xxx_INTR MDP_INTF2_INTR -#define MDP_INTF3_7xxx_INTR MDP_INTF3_INTR -#define MDP_INTF4_7xxx_INTR MDP_INTF4_INTR -#define MDP_INTF5_7xxx_INTR MDP_INTF5_INTR -#define MDP_INTF6_7xxx_INTR MDP_INTF6_INTR -#define MDP_INTF7_7xxx_INTR MDP_INTF7_INTR -#define MDP_INTF8_7xxx_INTR MDP_INTF8_INTR -#define MDP_INTF1_7xxx_TEAR_INTR MDP_INTF1_TEAR_INTR -#define MDP_INTF2_7xxx_TEAR_INTR MDP_INTF2_TEAR_INTR - #define DPU_IRQ_IDX(reg_idx, offset) (reg_idx * 32 + offset) /**