| Message ID | 20230808051407.647395-5-quic_imrashai@quicinc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add support for Qualcomm ECPRI clock controller | expand |
On 8.08.2023 07:14, Imran Shaik wrote: > Add device node for ECPRI clock controller on qcom QDU1000 > and QRU1000 SoCs. > > Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qdu1000.dtsi | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi > index 1c0e5d271e91..63930f944b65 100644 > --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi > +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi > @@ -381,6 +381,20 @@ gcc: clock-controller@80000 { > #power-domain-cells = <1>; > }; > > + ecpricc: clock-controller@280000 { > + compatible = "qcom,qdu1000-ecpricc"; > + reg = <0x0 0x00280000 0x0 0x31c00>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>, > + <&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>, > + <&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>, > + <&gcc GCC_ECPRI_CC_GPLL3_CLK_SRC>, > + <&gcc GCC_ECPRI_CC_GPLL4_CLK_SRC>, > + <&gcc GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC>; Please align the entries with the first < (probably missing a single space in the front) Konrad
On 8/10/2023 1:30 AM, Konrad Dybcio wrote: > On 8.08.2023 07:14, Imran Shaik wrote: >> Add device node for ECPRI clock controller on qcom QDU1000 >> and QRU1000 SoCs. >> >> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 14 ++++++++++++++ >> 1 file changed, 14 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi >> index 1c0e5d271e91..63930f944b65 100644 >> --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi >> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi >> @@ -381,6 +381,20 @@ gcc: clock-controller@80000 { >> #power-domain-cells = <1>; >> }; >> >> + ecpricc: clock-controller@280000 { >> + compatible = "qcom,qdu1000-ecpricc"; >> + reg = <0x0 0x00280000 0x0 0x31c00>; >> + clocks = <&rpmhcc RPMH_CXO_CLK>, >> + <&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>, >> + <&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>, >> + <&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>, >> + <&gcc GCC_ECPRI_CC_GPLL3_CLK_SRC>, >> + <&gcc GCC_ECPRI_CC_GPLL4_CLK_SRC>, >> + <&gcc GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC>; > Please align the entries with the first < (probably missing a single > space in the front) > > Konrad Sure, will update and push next series. Thanks, Imran
diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 1c0e5d271e91..63930f944b65 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -381,6 +381,20 @@ gcc: clock-controller@80000 { #power-domain-cells = <1>; }; + ecpricc: clock-controller@280000 { + compatible = "qcom,qdu1000-ecpricc"; + reg = <0x0 0x00280000 0x0 0x31c00>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>, + <&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>, + <&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>, + <&gcc GCC_ECPRI_CC_GPLL3_CLK_SRC>, + <&gcc GCC_ECPRI_CC_GPLL4_CLK_SRC>, + <&gcc GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + gpi_dma0: dma-controller@900000 { compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0x0 0x900000 0x0 0x60000>;
Add device node for ECPRI clock controller on qcom QDU1000 and QRU1000 SoCs. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)