| Message ID | 20230911221627.9569-1-quic_abhinavk@quicinc.com |
|---|---|
| State | Accepted |
| Commit | 10f20628c9b8e924b8046e63b36b2cea4d2c85e4 |
| Headers | show |
| Series | [v2,1/2] drm/msm/dpu: fail dpu_plane_atomic_check() based on mdp clk limits | expand |
On Tue, 12 Sept 2023 at 01:18, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote: > > Currently, dpu_plane_atomic_check() does not check whether the > plane can process the image without exceeding the per chipset > limits for MDP clock. This leads to underflow issues because the > SSPP is not able to complete the processing for the data rate of > the display. > > Fail the dpu_plane_atomic_check() if the SSPP cannot process the > image without exceeding the MDP clock limits. > > changes in v2: > - use crtc_state's adjusted_mode instead of mode > > Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") > Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 15 ++++++++++++--- > 1 file changed, 12 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > index 98c1b22e9bca..0be195f9149c 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > @@ -733,9 +733,11 @@ static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu, > static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, > struct dpu_sw_pipe *pipe, > struct dpu_sw_pipe_cfg *pipe_cfg, > - const struct dpu_format *fmt) > + const struct dpu_format *fmt, > + const struct drm_display_mode *mode) > { > uint32_t min_src_size; > + struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); > > min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1; > > @@ -774,6 +776,12 @@ static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, > return -EINVAL; > } > > + /* max clk check */ > + if (_dpu_plane_calc_clk(mode, pipe_cfg) > kms->perf.max_core_clk_rate) { > + DPU_DEBUG_PLANE(pdpu, "plane exceeds max mdp core clk limits\n"); > + return -E2BIG; > + } > + > return 0; > } > > @@ -899,12 +907,13 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, > r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2; > } > > - ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt); > + ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt, &crtc_state->adjusted_mode); > if (ret) > return ret; > > if (r_pipe->sspp) { > - ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt); > + ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt, > + &crtc_state->adjusted_mode); > if (ret) > return ret; > } > -- > 2.40.1 >
On Mon, 11 Sep 2023 15:16:26 -0700, Abhinav Kumar wrote: > Currently, dpu_plane_atomic_check() does not check whether the > plane can process the image without exceeding the per chipset > limits for MDP clock. This leads to underflow issues because the > SSPP is not able to complete the processing for the data rate of > the display. > > Fail the dpu_plane_atomic_check() if the SSPP cannot process the > image without exceeding the MDP clock limits. > > [...] Applied, thanks! [2/2] drm/msm/dpu: try multirect based on mdp clock limits https://gitlab.freedesktop.org/lumag/msm/-/commit/e6c0de5f4450 Best regards,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 98c1b22e9bca..0be195f9149c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -733,9 +733,11 @@ static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu, static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe, struct dpu_sw_pipe_cfg *pipe_cfg, - const struct dpu_format *fmt) + const struct dpu_format *fmt, + const struct drm_display_mode *mode) { uint32_t min_src_size; + struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1; @@ -774,6 +776,12 @@ static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, return -EINVAL; } + /* max clk check */ + if (_dpu_plane_calc_clk(mode, pipe_cfg) > kms->perf.max_core_clk_rate) { + DPU_DEBUG_PLANE(pdpu, "plane exceeds max mdp core clk limits\n"); + return -E2BIG; + } + return 0; } @@ -899,12 +907,13 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2; } - ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt); + ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt, &crtc_state->adjusted_mode); if (ret) return ret; if (r_pipe->sspp) { - ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt); + ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt, + &crtc_state->adjusted_mode); if (ret) return ret; }
Currently, dpu_plane_atomic_check() does not check whether the plane can process the image without exceeding the per chipset limits for MDP clock. This leads to underflow issues because the SSPP is not able to complete the processing for the data rate of the display. Fail the dpu_plane_atomic_check() if the SSPP cannot process the image without exceeding the MDP clock limits. changes in v2: - use crtc_state's adjusted_mode instead of mode Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-)