From patchwork Mon Oct 30 10:36:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 739321 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9422FC4167B for ; Mon, 30 Oct 2023 10:37:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232924AbjJ3KhB (ORCPT ); Mon, 30 Oct 2023 06:37:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232769AbjJ3Kgw (ORCPT ); Mon, 30 Oct 2023 06:36:52 -0400 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E692C5 for ; Mon, 30 Oct 2023 03:36:49 -0700 (PDT) Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-9d2e6c8b542so177020466b.0 for ; Mon, 30 Oct 2023 03:36:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698662208; x=1699267008; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=/2OV3dFd3+7TorEvOU5N+P3IiIqu2Ym8tmt4xBT5dwY=; b=WS9Qn+i0nDpSqMsMw+zeRAB/+9Qw7Tza/xBac7ScZQ/KCDEqbuRggFH8hoIPfaRnwt rLup9FfSwI5ekLPj9K4qKvy0Tq6j6w0BoFqueTqQJ26pifPk9+wrrxS+bzleSWDnnX0q /bJK69V1GUzWXAppklu2uTjpV2U7FZkTfySgXJxRSI4aN3PTIqYpVGVV6mZa+8fYwB2p rgW592EnibZ/zWMbzgSJmIgz/8YmhbpkE4Xqrco4kcHJKExe7PeLD1Rc3v07Xl7wmW2k zw/i5SctX2c6g8VXvzpbXmowO0A1s0NmjcZaDbVUwKA/wExn8tQqBoJfJ6Tqc9mS02xf OaMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698662208; x=1699267008; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/2OV3dFd3+7TorEvOU5N+P3IiIqu2Ym8tmt4xBT5dwY=; b=fRttTmzTarf/lvvf5mdvbKVub2UVhhnpgoDlO1zYRo5sHFXTGKIVRouvdYdB43gV/2 somPblRUrZhJG94jHHI2Jzrd1nylc9Ed0X0/MCi7GqfK+gpgExL9Zsp4vRCQ6sZ51o+8 LJOgii9MyKaUzpJdHINE6Jh5rK9ZHtspPEPyB+1rnHBVfaQJGkAh1eBTN8uDxFNBuB1M 9IGmulfKUOAzA0f3lSeMj/C8i07lX5/zu6XP1q4m4icUqrVYv5X/eXwci4a0JHTRA2p7 7sd8z6p+kRTCHbdfEW3QfvVWQvSY26YzXvBmBEVPP9aO14DjcY1yOFzKG/wkEaF8gBPz PzsA== X-Gm-Message-State: AOJu0YyF9tSd+uwZmmFH94KwQ8/PEWMnDn/150alr6EZbFBBl4MIwooX 5jGCc2oDJBjEhePykO4/VlqPtA== X-Google-Smtp-Source: AGHT+IGbohuifZxdIHZS+7iC4Bec7pebMWnxwr7udyRgN8X7IGEmpTDbsahkbZNb0WTqQevDmu6Isg== X-Received: by 2002:a17:907:6d05:b0:9ad:a59f:331a with SMTP id sa5-20020a1709076d0500b009ada59f331amr8837169ejc.57.1698662207859; Mon, 30 Oct 2023 03:36:47 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id r5-20020a05600c458500b004060f0a0fd5sm8783209wmo.13.2023.10.30.03.36.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 03:36:47 -0700 (PDT) From: Neil Armstrong Date: Mon, 30 Oct 2023 11:36:26 +0100 Subject: [PATCH v2 4/8] dt-bindings: display: msm: document the SM8650 Mobile Display Subsystem MIME-Version: 1.0 Message-Id: <20231030-topic-sm8650-upstream-mdss-v2-4-43f1887c82b8@linaro.org> References: <20231030-topic-sm8650-upstream-mdss-v2-0-43f1887c82b8@linaro.org> In-Reply-To: <20231030-topic-sm8650-upstream-mdss-v2-0-43f1887c82b8@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Marek , Krishna Manikandan Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Krzysztof Kozlowski X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=10135; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=5QSy/+cFPldX20Hrn2ch7mP7dFh0iNCAZ6kGBnX0PQ8=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBlP4c3jUDCuFVkbHOzdoHwJnB0gpTES2lOSXojetFp Wo6wNBWJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZT+HNwAKCRB33NvayMhJ0Qp2D/ 95tw4hcXAiNG3UuGhGR1y5plDzvFgMZ71RfW0A40SSN3qtzUpWtEtXAQmMdYk7rS8Wy3CVKHgjRc9M 2sFi3fbLdgqN8eT2TYNS0iKSNmKu00v8g+wgF2EvyoU6fMwC5wOi5x0mHwC3wPO56yqIpDAhI7xiA+ RDdE0WkbCPka9pmODQwOzPNILkiNTyuvsiMRenY7qbzVgg42CpFp5h93ry07p9pragA3eZv0CxDDrC HvEOzEdFnwN8KVuTuidRc08SiQHHNNIckDKjr1GpmrmwWpMJVfYfaMmH3orbXHI/3Q05OYpn2SNru/ S/4piyyL+XtlTEp/LU5LD2i6MWcD6bE+jNUZriwJmilisMY4E1XKj3AJWSQN4mL0wtYUG3F3GjD6un O267U/ftRy103QNU4+GdVPXYwcBS2f5kBRzWre9Tte/sHZIKPkeQjy5HtLEqp6Iv3dKO8DBKjgRFHg CbcH0af0nd5G9xGQqQgxzjEtBFZeYfg+Lo2Oo9aYPQbaC36VCY1t+KeaHV1c5nsqkN8zYrBIJivCN3 WOrTbKrNDXXSoCHVwO5Rb5AQlGDOXEmzbnLidNa83N+S6CHI+D1WN4Iwnnpc9X18S5ssDinnl5cZuL 6ME7Zgl0zw0HXtSZT+gMqbloFL0vPblBdLlYtP2mzKivdjviEmPzIMcxFF4w== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document the Mobile Display Subsystem (MDSS) on the SM8650 Platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong --- .../bindings/display/msm/qcom,sm8650-mdss.yaml | 322 +++++++++++++++++++++ 1 file changed, 322 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-mdss.yaml new file mode 100644 index 000000000000..5638c1ea692e --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-mdss.yaml @@ -0,0 +1,322 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8650-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8650 Display MDSS + +maintainers: + - Neil Armstrong + +description: + SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like + DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sm8650-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm8650-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + items: + - const: qcom,sm8650-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm8650-dsi-phy-4nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + display-subsystem@ae00000 { + compatible = "qcom,sm8650-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + resets = <&dispcc_core_bcr>; + + power-domains = <&dispcc_gdsc>; + + clocks = <&gcc_ahb_clk>, + <&gcc_axi_clk>, + <&dispcc_mdp_clk>; + clock-names = "bus", "nrt_bus", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x1c00 0x2>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sm8650-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc_axi_clk>, + <&dispcc_ahb_clk>, + <&dispcc_mdp_lut_clk>, + <&dispcc_mdp_clk>, + <&dispcc_mdp_vsync_clk>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc_mdp_vsync_clk>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz = /bits/ 64 <514000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispc_byte_clk>, + <&dispcc_intf_clk>, + <&dispcc_pclk>, + <&dispcc_esc_clk>, + <&dispcc_ahb_clk>, + <&gcc_bus_clk>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc_byte_clk>, + <&dispcc_pclk>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + dsi0_phy: phy@ae94400 { + compatible = "qcom,sm8650-dsi-phy-4nm"; + reg = <0x0ae95000 0x200>, + <0x0ae95200 0x280>, + <0x0ae95500 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc_iface_clk>, + <&rpmhcc_ref_clk>; + clock-names = "iface", "ref"; + }; + + dsi@ae96000 { + compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispc_byte_clk>, + <&dispcc_intf_clk>, + <&dispcc_pclk>, + <&dispcc_esc_clk>, + <&dispcc_ahb_clk>, + <&gcc_bus_clk>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc_byte_clk>, + <&dispcc_pclk>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: phy@ae96400 { + compatible = "qcom,sm8650-dsi-phy-4nm"; + reg = <0x0ae97000 0x200>, + <0x0ae97200 0x280>, + <0x0ae97500 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc_iface_clk>, + <&rpmhcc_ref_clk>; + clock-names = "iface", "ref"; + }; + }; +...