From patchwork Fri Nov 17 10:56:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 744689 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="C6vHr2Sj" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C1D21AD; Fri, 17 Nov 2023 02:57:34 -0800 (PST) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AHAvMi5001496; Fri, 17 Nov 2023 10:57:22 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=XGbNMyyEP5Khovrq8/HtXCI77+Ikuwg3J7EWBFyTJiA=; b=C6vHr2SjLfNcjF8QRMKh3JeK7R+qFTd9pUhdaPbN4kyYkZqJkzy4C1xQ8EaFvrgiI77o VAbWb34MIV9RnqL6GB4p9OTRBsnixDRp+1jr9dW2JVbtPcfCWctK6Glsk58qPp/UvOEl 4HfM2zjM+R1PvKVkPQSRv106OsH4aFYsTh/Il/sJgghW41eMJcHleIRm/8zyH8q7sS4w hJbvjM25S+s+fcMvzxAHFd66BW2y0mwKmuoo1uh/X8SRKHFHMXvIkZX/Gwu2BfXg1cPT qWmFmEbaBD+Sg4aikvLDyHxoCh9sc4Zwk3nE4I4Hvn1hDEQ8nzvbUfjAom5srxgxXbxo 2w== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3udt8bsgam-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Nov 2023 10:57:21 +0000 Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AHAvL2R016325 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Nov 2023 10:57:21 GMT Received: from blr-ubuntu-87.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Fri, 17 Nov 2023 02:57:14 -0800 From: Sibi Sankar To: , , , , , , CC: , , , , , , , , , , , , , Sibi Sankar Subject: [PATCH V2 1/4] dt-bindings: arm-smmu: Add compatible for X1E80100 SoC Date: Fri, 17 Nov 2023 16:26:32 +0530 Message-ID: <20231117105635.343-2-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231117105635.343-1-quic_sibis@quicinc.com> References: <20231117105635.343-1-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 6q_CK0Uc8CwezXSwtb0sqMzcVXcluoCd X-Proofpoint-GUID: 6q_CK0Uc8CwezXSwtb0sqMzcVXcluoCd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-17_09,2023-11-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 priorityscore=1501 suspectscore=0 mlxscore=0 mlxlogscore=963 adultscore=0 bulkscore=0 malwarescore=0 spamscore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311170081 From: Rajendra Nayak Add the SoC specific compatible for X1E80100 implementing arm,mmu-500. Signed-off-by: Rajendra Nayak Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Reviewed-by: Krzysztof Kozlowski --- v2: * Update the part number from sc8380xp to x1e80100. * Pickup Rbs. Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index aa9e1c0895a5..7ae4f65fe236 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -56,6 +56,7 @@ properties: - qcom,sm8350-smmu-500 - qcom,sm8450-smmu-500 - qcom,sm8550-smmu-500 + - qcom,x1e80100-smmu-500 - const: qcom,smmu-500 - const: arm,mmu-500 @@ -475,6 +476,7 @@ allOf: - qcom,sm8350-smmu-500 - qcom,sm8450-smmu-500 - qcom,sm8550-smmu-500 + - qcom,x1e80100-smmu-500 then: properties: clock-names: false