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Fri, 26 Jan 2024 02:00:48 -0800 (PST) Received: from [127.0.1.1] ([79.115.23.25]) by smtp.gmail.com with ESMTPSA id ox27-20020a170907101b00b00a3221b95ce8sm448494ejb.77.2024.01.26.02.00.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 02:00:47 -0800 (PST) From: Abel Vesa Date: Fri, 26 Jan 2024 12:00:22 +0200 Subject: [PATCH v5 11/11] arm64: dts: qcom: x1e80100-qcp: Fix supplies for LDOs 3E and 2J Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240126-x1e80100-dts-missing-nodes-v5-11-3bb716fb2af9@linaro.org> References: <20240126-x1e80100-dts-missing-nodes-v5-0-3bb716fb2af9@linaro.org> In-Reply-To: <20240126-x1e80100-dts-missing-nodes-v5-0-3bb716fb2af9@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Rajendra Nayak Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The LDOs 3E and 2J are actually supplied by SMPS 5J. Fix accordingly. Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Acked-by: Konrad Dybcio Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 8dbf6d0eaac3..e76d29053d79 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -261,7 +261,7 @@ regulators-3 { qcom,pmic-id = "e"; vdd-l2-supply = <&vreg_s1f_0p7>; - vdd-l3-supply = <&vph_pwr>; + vdd-l3-supply = <&vreg_s5j_1p2>; vreg_l2e_0p8: ldo2 { regulator-name = "vreg_l2e_0p8"; @@ -367,7 +367,7 @@ regulators-7 { qcom,pmic-id = "j"; vdd-l1-supply = <&vreg_s1f_0p7>; - vdd-l2-supply = <&vph_pwr>; + vdd-l2-supply = <&vreg_s5j_1p2>; vdd-l3-supply = <&vreg_s1f_0p7>; vdd-s5-supply = <&vph_pwr>;