From patchwork Thu Feb 8 23:13:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wesley Cheng X-Patchwork-Id: 771941 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A3F650A83; Thu, 8 Feb 2024 23:14:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707434081; cv=none; b=TdRTpLVS4f3fMOlhEAsWNkXL4POTdG+wWBkwrLi1/1P2SIn7xsQWWZIKrYHPsvCo+crGXGCyM0KGK16osNDmRmfx5qgpU1S3XVSuPGauMNMTOEn3INz+9n6pgBKlE1yUOKZF4HHnt1QBl0G9RLId+VYQjMw/IPcIsLgopKCw25Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707434081; c=relaxed/simple; bh=+Lw1+4MAX2LtZpd2jn62R4vA+ALFex1PxyuYDKU/fN0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=atVKWWjdCr+Dsqmdzy7G4+3jAdV/QZwzpSfIrxbjEGjDebKfN2grV+XR/o4tEXo+OQdch/FC9G8HTo2hebM23oqpkxhgUzEBhXLaWn7w07fSa4CdYZdJkyB/2QpGAYJY/i/wUcEqwLFqWXkxiKI1g040sCl5uQYnRlOpeLHKmWw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=mqP9cIx0; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="mqP9cIx0" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 418MmN3S002112; Thu, 8 Feb 2024 23:14:18 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=qcppdkim1; bh=CAxjiLONN0FsfVJGEMs1 T7t8zj114/9U4ixQ4PoMPaY=; b=mqP9cIx0InFl7OdHAQAPRVMprKdpURH8hyxv UkPKn/HWmUHuuA4F+zYlg1O5JcoK+ZFTzUjtOSf8gaL3aXDNUH2JT0tky+Rf4nqr IABYPGzZ8jiD1Kn5mskLYL+gwVfF+Gdyny3J35ZTx1AQsVYwv9DUaWY7dG1Ifen0 mCMe8b1bG1h1y5CxnrIT8KoRQU03gemSmR3OFof3tyNWnq6RoqZmsvk51ngGXCmu ffuWPcmDxPpwrCoesUIRfPJ7m12Hnnz/o2MMra5UcXurAI4/kYD+FedAedqwAQSZ i8bfMIfweDzyvqrG9c7Ed+IU4VGhjcJZsgXGALQuWiI5rPPjew== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3w4frwujtu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 08 Feb 2024 23:14:17 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 418NEGLm013078 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 8 Feb 2024 23:14:16 GMT Received: from hu-wcheng-lv.qualcomm.com (10.49.16.6) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 8 Feb 2024 15:14:16 -0800 From: Wesley Cheng To: , , , , , , , , , , , , , , CC: , , , , , , , Mathias Nyman , Wesley Cheng Subject: [PATCH v14 03/53] xhci: Add interrupt pending autoclear flag to each interrupter Date: Thu, 8 Feb 2024 15:13:16 -0800 Message-ID: <20240208231406.27397-4-quic_wcheng@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240208231406.27397-1-quic_wcheng@quicinc.com> References: <20240208231406.27397-1-quic_wcheng@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: jV9Z2PR1PTwfQH0bOBidFR4StK83vaMM X-Proofpoint-GUID: jV9Z2PR1PTwfQH0bOBidFR4StK83vaMM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-08_11,2024-02-08_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 spamscore=0 suspectscore=0 bulkscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=742 adultscore=0 priorityscore=1501 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402080131 From: Mathias Nyman Each interrupter has an interrupt pending (IP) bit that should be cleared in the interrupt handler. This is done automatically for systems using MSI/MSI-X interrupts. Secondary interrupters used by audio offload may not actually trigger MSI/MSI-X messages, so driver may need to clear the IP bit manually for these, even if the primary interrupter IP is cleared automatically. Add an ip_autoclear flag to each interrupter that driver can configure when requesting an interrupt for that xHC interrupter, and move the interrupt pending clearing code to its own helper function. Use this ip_autoclear flag instead of the current hcd->msi_enabled to check if IP flag is cleared by software. [Moved ip_autoclear into xhci and set based on msi_enabled -wcheng] Signed-off-by: Mathias Nyman Signed-off-by: Wesley Cheng --- drivers/usb/host/xhci-ring.c | 21 +++++++++++++++------ drivers/usb/host/xhci.c | 3 +++ drivers/usb/host/xhci.h | 1 + 3 files changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 33806ae966f9..f8e78068c36f 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -3013,6 +3013,19 @@ static void xhci_update_erst_dequeue(struct xhci_hcd *xhci, xhci_write_64(xhci, temp_64, &ir->ir_set->erst_dequeue); } +/* Clear the interrupt pending bit for a specific interrupter. */ +static void xhci_clear_interrupt_pending(struct xhci_hcd *xhci, + struct xhci_interrupter *ir) +{ + if (!ir->ip_autoclear) { + u32 irq_pending; + + irq_pending = readl(&ir->ir_set->irq_pending); + irq_pending |= IMAN_IP; + writel(irq_pending, &ir->ir_set->irq_pending); + } +} + /* * xHCI spec says we can get an interrupt, and if the HC has an error condition, * we might get bad data out of the event ring. Section 4.10.2.7 has a list of @@ -3062,12 +3075,8 @@ irqreturn_t xhci_irq(struct usb_hcd *hcd) /* This is the handler of the primary interrupter */ ir = xhci->interrupters[0]; - if (!hcd->msi_enabled) { - u32 irq_pending; - irq_pending = readl(&ir->ir_set->irq_pending); - irq_pending |= IMAN_IP; - writel(irq_pending, &ir->ir_set->irq_pending); - } + + xhci_clear_interrupt_pending(xhci, ir); if (xhci->xhc_state & XHCI_STATE_DYING || xhci->xhc_state & XHCI_STATE_HALTED) { diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index c057c42c36f4..0886829d53e5 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -538,6 +538,9 @@ int xhci_run(struct usb_hcd *hcd) */ hcd->uses_new_polling = 1; + if (hcd->msi_enabled) + ir->ip_autoclear = true; + if (!usb_hcd_is_primary_hcd(hcd)) return xhci_run_finished(xhci); diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index c6349e7e1e95..daee202cd369 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1431,6 +1431,7 @@ struct xhci_interrupter { struct xhci_erst erst; struct xhci_intr_reg __iomem *ir_set; unsigned int intr_num; + bool ip_autoclear; /* For interrupter registers save and restore over suspend/resume */ u32 s3_irq_pending; u32 s3_irq_control;