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[37.8.245.233]) by smtp.gmail.com with ESMTPSA id gz9-20020a170906f2c900b00a3515b35be4sm193052ejb.104.2024.02.12.05.10.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 05:10:23 -0800 (PST) From: Konrad Dybcio Date: Mon, 12 Feb 2024 14:10:11 +0100 Subject: [PATCH 3/7] arm64: dts: qcom: sm8550: Mark QUPs and GPI dma-coherent Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240210-topic-1v-v1-3-fda0db38e29b@linaro.org> References: <20240210-topic-1v-v1-0-fda0db38e29b@linaro.org> In-Reply-To: <20240210-topic-1v-v1-0-fda0db38e29b@linaro.org> To: James Schulman , David Rhodes , Richard Fitzgerald , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ricardo Rivera-Matos , Bjorn Andersson , Abel Vesa , Sai Prakash Ranjan , Neil Armstrong , Kees Cook , Tony Luck , "Guilherme G. Piccoli" Cc: Marijn Suijten , alsa-devel@alsa-project.org, patches@opensource.cirrus.com, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1707743413; l=1550; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=OOS7lbYOFBWS9cWYXmiccxamzx9nSjNqu+J04bjACok=; b=H1Bcg2rzFfpWZ+ONZTsv+XotMsPZWzH0sPWJa5fy6xS93138s4pZiqOTYI7h7EjM4AclTuj9G +Ermko5L4yxCW2wmwFkyuUOJYChewCVx9fjKmkcNEtaHvWwgWA+efNV X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= These peripherals are DMA-coherent on 8550. Mark them as such. Interestingly enough, the I2C master hubs are not. Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index b8f1c7f97e48..d696ec6c6850 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -812,6 +812,7 @@ gpi_dma2: dma-controller@800000 { dma-channels = <12>; dma-channel-mask = <0x3e>; iommus = <&apps_smmu 0x436 0>; + dma-coherent; status = "disabled"; }; @@ -823,6 +824,7 @@ qupv3_id_1: geniqup@8c0000 { clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; iommus = <&apps_smmu 0x423 0>; + dma-coherent; #address-cells = <2>; #size-cells = <2>; status = "disabled"; @@ -1322,6 +1324,7 @@ gpi_dma1: dma-controller@a00000 { dma-channels = <12>; dma-channel-mask = <0x1e>; iommus = <&apps_smmu 0xb6 0>; + dma-coherent; status = "disabled"; }; @@ -1335,6 +1338,7 @@ qupv3_id_0: geniqup@ac0000 { iommus = <&apps_smmu 0xa3 0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; interconnect-names = "qup-core"; + dma-coherent; #address-cells = <2>; #size-cells = <2>; status = "disabled";