[17/21] ARM: dts: qcom: ipq8064: Add PCIe bridge node

Message ID	20240221-pcie-qcom-bridge-dts-v1-17-6c6df0f9450d@linaro.org
State	Superseded
Headers	show Received: from mail-pf1-f169.google.com (mail-pf1-f169.google.com [209.85.210.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C60A03F9EC for <linux-arm-msm@vger.kernel.org>; Wed, 21 Feb 2024 03:43:07 +0000 (UTC) From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Date: Wed, 21 Feb 2024 09:12:03 +0530 Subject: [PATCH 17/21] ARM: dts: qcom: ipq8064: Add PCIe bridge node Precedence: bulk MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20240221-pcie-qcom-bridge-dts-v1-17-6c6df0f9450d@linaro.org> References: <20240221-pcie-qcom-bridge-dts-v1-0-6c6df0f9450d@linaro.org> In-Reply-To: <20240221-pcie-qcom-bridge-dts-v1-0-6c6df0f9450d@linaro.org> To: Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Series	Add PCIe bridge node in DT for Qcom SoCs \| expand [00/21] Add PCIe bridge node in DT for Qcom SoCs [01/21] arm64: dts: qcom: sm8250: Add PCIe bridge node [02/21] arm64: dts: qcom: sdm845: Add PCIe bridge node [03/21] arm64: dts: qcom: sm8150: Add PCIe bridge node [04/21] arm64: dts: qcom: sm8350: Add PCIe bridge node [05/21] arm64: dts: qcom: sm8450: Add PCIe bridge node [06/21] arm64: dts: qcom: sm8550: Add PCIe bridge node [07/21] arm64: dts: qcom: sm8650: Add PCIe bridge node [08/21] arm64: dts: qcom: sa8775p: Add PCIe bridge node [09/21] arm64: dts: qcom: sc8280xp: Add PCIe bridge node [10/21] arm64: dts: qcom: msm8998: Add PCIe bridge node [11/21] arm64: dts: qcom: sc7280: Add PCIe bridge node [12/21] arm64: dts: qcom: qcs404: Add PCIe bridge node [13/21] arm64: dts: qcom: sc8180x: Add PCIe bridge node [14/21] arm64: dts: qcom: msm8996: Add PCIe bridge node [15/21] arm64: dts: qcom: ipq8074: Add PCIe bridge node [16/21] arm64: dts: qcom: ipq6018: Add PCIe bridge node [17/21] ARM: dts: qcom: ipq8064: Add PCIe bridge node [18/21] ARM: dts: qcom: ipq4019: Add PCIe bridge node [19/21] ARM: dts: qcom: apq8064: Add PCIe bridge node [20/21] ARM: dts: qcom: sdx55: Add PCIe bridge node [21/21] arm64: dts: qcom: sm8650: Use "pcie" as the node name instead of "pci"

Message ID

20240221-pcie-qcom-bridge-dts-v1-17-6c6df0f9450d@linaro.org

State

Superseded

Headers

From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Date: Wed, 21 Feb 2024 09:12:03 +0530
Subject: [PATCH 17/21] ARM: dts: qcom: ipq8064: Add PCIe bridge node
Precedence: bulk
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Message-Id: <20240221-pcie-qcom-bridge-dts-v1-17-6c6df0f9450d@linaro.org>
References: <20240221-pcie-qcom-bridge-dts-v1-0-6c6df0f9450d@linaro.org>
In-Reply-To: <20240221-pcie-qcom-bridge-dts-v1-0-6c6df0f9450d@linaro.org>
To: Bjorn Andersson <andersson@kernel.org>,
 Konrad Dybcio <konrad.dybcio@linaro.org>, Rob Herring <robh+dt@kernel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
 Conor Dooley <conor+dt@kernel.org>, cros-qcom-dts-watchers@chromium.org
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
 linux-kernel@vger.kernel.org,
 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Series

Add PCIe bridge node in DT for Qcom SoCs | expand

Commit Message

Manivannan Sadhasivam Feb. 21, 2024, 3:42 a.m. UTC

On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
index 6a7f4dd0f775..98448ea6ffca 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
@@ -1125,6 +1125,16 @@  pcie0: pcie@1b500000 {
 
 			status = "disabled";
 			perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
+
+			pcie@0 {
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				bus-range = <0x01 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
 		};
 
 		pcie1: pcie@1b700000 {
@@ -1176,6 +1186,16 @@  pcie1: pcie@1b700000 {
 
 			status = "disabled";
 			perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
+
+			pcie@0 {
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				bus-range = <0x01 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
 		};
 
 		pcie2: pcie@1b900000 {
@@ -1227,6 +1247,16 @@  pcie2: pcie@1b900000 {
 
 			status = "disabled";
 			perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
+
+			pcie@0 {
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				bus-range = <0x01 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
 		};
 
 		qsgmii_csr: syscon@1bb00000 {

[17/21] ARM: dts: qcom: ipq8064: Add PCIe bridge node

Commit Message

Patch