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Tue, 20 Feb 2024 19:42:29 -0800 (PST) Received: from [127.0.1.1] ([117.207.28.224]) by smtp.gmail.com with ESMTPSA id o23-20020a056a001b5700b006e466369645sm4436231pfv.132.2024.02.20.19.42.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Feb 2024 19:42:28 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 21 Feb 2024 09:11:52 +0530 Subject: [PATCH 06/21] arm64: dts: qcom: sm8550: Add PCIe bridge node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240221-pcie-qcom-bridge-dts-v1-6-6c6df0f9450d@linaro.org> References: <20240221-pcie-qcom-bridge-dts-v1-0-6c6df0f9450d@linaro.org> In-Reply-To: <20240221-pcie-qcom-bridge-dts-v1-0-6c6df0f9450d@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1223; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=J3jKul/0PQXElhNJclej25sO29NA0XDyDmSBGcZmLg4=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBl1XEGLKuGwuIxVfZ2RAl8RPL9QF7taAoLBqgS3 rAp1TV+/q2JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZdVxBgAKCRBVnxHm/pHO 9d9RB/4mKO61dfmraNPj60rQK3e6WYHIT/rny685M0kxYOBK6saH/jo5Y5hDv4vWoBTUrthxCRn s4uhfwePoyfGLdaLZcg8vK59hXliyzLmhT9nG5scCP5VfF8+4kOaYpTzFCGG9zjCFuYFEuu6Itn MKvgyo8mJjALR7uJVCTFqBCj740N0c1lRxo/0zvngJ3dP5ipJmBvdUDUH5+dtqgtB4ylHqUnTvE 5iH0CgMUOMk/i6VUqN/VNIy6jtKDDkvlNvfcy0whCx1ZcZvNY2lq62n5JaBpO1tYCu/d9OHFQPl ORvFjlLFZtfm0K5GsXjxl+JUMxDDIVdZdXFlsNOafSnv88w7 X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index ee1ba5a8c8fc..3ee11311885f 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1754,6 +1754,16 @@ pcie0: pcie@1c00000 { phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -1851,6 +1861,16 @@ pcie1: pcie@1c08000 { phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 {