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Tue, 30 Apr 2024 14:30:33 GMT Received: from hu-jkona-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 30 Apr 2024 07:30:28 -0700 From: Jagadeesh Kona To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Vladimir Zapolskiy CC: Bryan O'Donoghue , , , , , Taniya Das , Jagadeesh Kona , "Satya Priya Kakitapalli" , Ajit Pandey , Imran Shaik , "Dmitry Baryshkov" Subject: [PATCH V3 3/8] clk: qcom: videocc-sm8550: Add support for videocc XO clk ares Date: Tue, 30 Apr 2024 19:57:52 +0530 Message-ID: <20240430142757.16872-4-quic_jkona@quicinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240430142757.16872-1-quic_jkona@quicinc.com> References: <20240430142757.16872-1-quic_jkona@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: GB1ckkfAUYMPR-G461qCFop5mRbmJ4t- X-Proofpoint-ORIG-GUID: GB1ckkfAUYMPR-G461qCFop5mRbmJ4t- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-04-30_08,2024-04-30_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 mlxlogscore=999 priorityscore=1501 phishscore=0 mlxscore=0 adultscore=0 bulkscore=0 clxscore=1011 suspectscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404300103 Add support for videocc XO clk ares for consumer drivers to be able to request this reset. Fixes: f53153a37969 ("clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550") Signed-off-by: Jagadeesh Kona Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/videocc-sm8550.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c index d73f747d2474..25133cf5a2b8 100644 --- a/drivers/clk/qcom/videocc-sm8550.c +++ b/drivers/clk/qcom/videocc-sm8550.c @@ -10,7 +10,7 @@ #include #include -#include +#include #include "clk-alpha-pll.h" #include "clk-branch.h" @@ -380,6 +380,7 @@ static const struct qcom_reset_map video_cc_sm8550_resets[] = { [CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 }, [VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0x8064, .bit = 2, .udelay = 1000 }, [VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x8090, .bit = 2, .udelay = 1000 }, + [VIDEO_CC_XO_CLK_ARES] = { .reg = 0x8124, .bit = 2, .udelay = 100 }, }; static const struct regmap_config video_cc_sm8550_regmap_config = {