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Fri, 31 May 2024 06:53:09 -0700 (PDT) Received: from [127.0.1.1] ([110.93.11.116]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4212b85ec87sm26762735e9.27.2024.05.31.06.53.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 May 2024 06:53:08 -0700 (PDT) From: Krzysztof Kozlowski Date: Fri, 31 May 2024 15:52:33 +0200 Subject: [PATCH 15/16] dt-bindings: clock: qcom,sm8550-dispcc: reference qcom,gcc.yaml Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240531-dt-bindings-qcom-gcc-v1-15-b37d49fe1421@linaro.org> References: <20240531-dt-bindings-qcom-gcc-v1-0-b37d49fe1421@linaro.org> In-Reply-To: <20240531-dt-bindings-qcom-gcc-v1-0-b37d49fe1421@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Konrad Dybcio , Jonathan Marek , Del Regno , Loic Poulain , Dmitry Baryshkov , Neil Armstrong , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Just like most of clock controllers, the SM8550 Display clock controller is also some variant of standard Qualcomm GCC, so reference common qcom,gcc.yaml schema to simplify the binding and unify it with others. Signed-off-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,sm8550-dispcc.yaml | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml index bad0260764d4..c17035a180db 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml @@ -45,18 +45,6 @@ properties: - description: Link clock from DP PHY3 - description: VCO DIV clock from DP PHY3 - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - power-domains: description: A phandle and PM domain specifier for the MMCX power domain. @@ -69,13 +57,13 @@ properties: required: - compatible - - reg - clocks - - '#clock-cells' - - '#reset-cells' - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - |