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[2a01:cb08:508:df00:ca96:65ff:fed2:3409]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42ca0600651sm90883925e9.32.2024.09.08.15.40.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Sep 2024 15:40:56 -0700 (PDT) From: =?utf-8?q?J=C3=A9r=C3=B4me_de_Bretagne?= To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Johan Hovold , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Maximilian Luz Subject: [PATCH v2 4/5] arm64: dts: qcom: sc8280xp: Add uart18 Date: Mon, 9 Sep 2024 00:35:04 +0200 Message-ID: <20240908223505.21011-5-jerome.debretagne@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240908223505.21011-1-jerome.debretagne@gmail.com> References: <20240908223505.21011-1-jerome.debretagne@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the node describing uart18 for sc8280xp devices. Signed-off-by: Jérôme de Bretagne --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 48 ++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 14c3b1d6ad47..1e520113db07 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1013,6 +1013,24 @@ spi18: spi@888000 { status = "disabled"; }; + uart18: serial@888000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00888000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interrupts = ; + operating-points-v2 = <&qup_opp_table_100mhz>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; + interconnect-names = "qup-core", "qup-config"; + + pinctrl-0 = <&qup_uart18_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + i2c19: i2c@88c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0088c000 0 0x4000>; @@ -4957,6 +4975,36 @@ cci3_i2c1_sleep: cci3-i2c1-sleep-pins { bias-pull-down; }; }; + + qup_uart18_default: qup-uart18-default-state { + cts-pins { + pins = "gpio66"; + function = "qup18"; + drive-strength = <2>; + bias-disable; + }; + + rts-pins { + pins = "gpio67"; + function = "qup18"; + drive-strength = <2>; + bias-disable; + }; + + tx-pins { + pins = "gpio68"; + function = "qup18"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio69"; + function = "qup18"; + drive-strength = <2>; + bias-disable; + }; + }; }; apps_smmu: iommu@15000000 {