[v8,04/12] drm/msm: Add CONTEXT_SWITCH_CNTL bitfields

Message ID	20241003-preemption-a750-t-v8-4-5c6cb9f256e0@gmail.com
State	Accepted
Commit	c7546e2c3cb739a3c1a2f5acaf9bb629d401afe5
Headers	show Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4E461A725E; Thu, 3 Oct 2024 16:13:05 +0000 (UTC) From: Antonino Maniscalco <antomani103@gmail.com> Date: Thu, 03 Oct 2024 18:12:53 +0200 Subject: [PATCH v8 04/12] drm/msm: Add CONTEXT_SWITCH_CNTL bitfields Precedence: bulk MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20241003-preemption-a750-t-v8-4-5c6cb9f256e0@gmail.com> References: <20241003-preemption-a750-t-v8-0-5c6cb9f256e0@gmail.com> In-Reply-To: <20241003-preemption-a750-t-v8-0-5c6cb9f256e0@gmail.com> To: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>, Konrad Dybcio <konrad.dybcio@linaro.org>, Abhinav Kumar <quic_abhinavk@quicinc.com>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, Marijn Suijten <marijn.suijten@somainline.org>, David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>, Maarten Lankhorst <maarten.lankhorst@linux.intel.com>, Maxime Ripard <mripard@kernel.org>, Thomas Zimmermann <tzimmermann@suse.de>, Jonathan Corbet <corbet@lwn.net> Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Antonino Maniscalco <antomani103@gmail.com>, Neil Armstrong <neil.armstrong@linaro.org>
Series	Preemption support for A7XX \| expand [v8,00/12] Preemption support for A7XX [v8,01/12] drm/msm: Fix bv_fence being used as bv_rptr [v8,02/12] drm/msm/a6xx: Track current_ctx_seqno per ring [v8,03/12] drm/msm: Add a `preempt_record_size` field [v8,04/12] drm/msm: Add CONTEXT_SWITCH_CNTL bitfields [v8,05/12] drm/msm/a6xx: Add a pwrup_list field to a6xx_info [v8,06/12] drm/msm/a6xx: Implement preemption for a7xx targets [v8,07/12] drm/msm/a6xx: Sync relevant adreno_pm4.xml changes [v8,08/12] drm/msm/a6xx: Use posamble to reset counters on preemption [v8,09/12] drm/msm/a6xx: Add traces for preemption [v8,10/12] drm/msm/a6xx: Add a flag to allow preemption to submitqueue_create [v8,11/12] drm/msm/a6xx: Enable preemption for tested a7xx targets [v8,12/12] Documentation: document adreno preemption

Message ID

20241003-preemption-a750-t-v8-4-5c6cb9f256e0@gmail.com

State

Accepted

Commit

c7546e2c3cb739a3c1a2f5acaf9bb629d401afe5

Headers

From: Antonino Maniscalco <antomani103@gmail.com>
Date: Thu, 03 Oct 2024 18:12:53 +0200
Subject: [PATCH v8 04/12] drm/msm: Add CONTEXT_SWITCH_CNTL bitfields
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Message-Id: <20241003-preemption-a750-t-v8-4-5c6cb9f256e0@gmail.com>
References: <20241003-preemption-a750-t-v8-0-5c6cb9f256e0@gmail.com>
In-Reply-To: <20241003-preemption-a750-t-v8-0-5c6cb9f256e0@gmail.com>
To: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
 Konrad Dybcio <konrad.dybcio@linaro.org>,
 Abhinav Kumar <quic_abhinavk@quicinc.com>,
 Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
 Marijn Suijten <marijn.suijten@somainline.org>,
 David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
 Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
 Maxime Ripard <mripard@kernel.org>, Thomas Zimmermann <tzimmermann@suse.de>,
 Jonathan Corbet <corbet@lwn.net>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
 freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org,
 linux-doc@vger.kernel.org, Antonino Maniscalco <antomani103@gmail.com>,
 Neil Armstrong <neil.armstrong@linaro.org>

Series

Preemption support for A7XX | expand

Commit Message

Antonino Maniscalco Oct. 3, 2024, 4:12 p.m. UTC

Add missing bitfields to CONTEXT_SWITCH_CNTL in a6xx.xml.

Tested-by: Rob Clark <robdclark@gmail.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8450-HDK
Signed-off-by: Antonino Maniscalco <antomani103@gmail.com>
---
 drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
index 2dfe6913ab4f52449b76c2f75b2d101c08115d16..fd31d1d7a11eef7f38dcc2975dc1034f6b7a2e41 100644
--- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
+++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
@@ -1337,7 +1337,12 @@  to upconvert to 32b float internally?
 		<reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
 	</array>
 
-	<reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/>
+	<reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL">
+		<bitfield name="STOP" pos="0" type="boolean"/>
+		<bitfield name="LEVEL" low="6" high="7"/>
+		<bitfield name="USES_GMEM" pos="8" type="boolean"/>
+		<bitfield name="SKIP_SAVE_RESTORE" pos="9" type="boolean"/>
+	</reg32>
 	<reg64 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO"/>
 	<reg64 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR"/>
 	<reg64 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR"/>

[v8,04/12] drm/msm: Add CONTEXT_SWITCH_CNTL bitfields

Commit Message

Patch