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[135.19.110.125]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6cbe8608e2csm31821496d6.102.2024.10.12.22.22.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Oct 2024 22:22:42 -0700 (PDT) From: Jonathan Marek To: linux-arm-msm@vger.kernel.org Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 4/5] arm64: dts: qcom: x1e80100-crd: add rtc offset to set rtc time Date: Sun, 13 Oct 2024 01:15:29 -0400 Message-ID: <20241013051859.22800-5-jonathan@marek.ca> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20241013051859.22800-1-jonathan@marek.ca> References: <20241013051859.22800-1-jonathan@marek.ca> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 See commit e67b45582c5e for explanation. Note: the 0xbc offset is arbitrary, it just needs to not be already in use. Signed-off-by: Jonathan Marek --- arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts index 6dfc85eda3540..eb6b735c41453 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -1224,6 +1224,17 @@ edp_bl_en: edp-bl-en-state { }; }; +&pmk8550_rtc { + nvmem-cells = <&rtc_offset>; + nvmem-cell-names = "offset"; +}; + +&pmk8550_sdam_2 { + rtc_offset: rtc-offset@bc { + reg = <0xbc 0x4>; + }; +}; + &qupv3_0 { status = "okay"; };