From patchwork Mon Oct 28 20:24:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Petrous via B4 Relay X-Patchwork-Id: 839391 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 063AF1DFDB1; Mon, 28 Oct 2024 20:25:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730147128; cv=none; b=tMZqBbxcdf9LiFbDi6okjrbkvnNKjdgBJTGQZLPWZzhPfVvlkMV3+mkq/+ymxgYRmDfHi5jY0SXnlCnT+m8Oh/ozlfDjG4c6oBiImkp8pbL07/bVnQcax9yjPI24TUEPLN17Qwhd83G5mOLxf/MDf5YKtgr2tbR6SSyMmVpVrlI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730147128; c=relaxed/simple; bh=/HY98JCmDq6A/RzqUc/7qBJZ10w18XtngjjYcjamv2s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NocYtNG0ZQYEav/hty3NNscNTsEqpkDt0uE2LOnlqCvNdGG5360dWDrJWTlk20lSRgFR3Mr6pvCmdK2fawn7LqS9kTBRazUUGFJJ+RVX6ibRN+lji4orax53a0m3sf4nRZD7LfQJ8ab8MJK8JoW2oX/2dFYYsoy9GBDnFEPrvuA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WX+E3Ik/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WX+E3Ik/" Received: by smtp.kernel.org (Postfix) with ESMTPS id 59C06C4CEEB; Mon, 28 Oct 2024 20:25:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1730147127; bh=/HY98JCmDq6A/RzqUc/7qBJZ10w18XtngjjYcjamv2s=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=WX+E3Ik/uBCXR8/6xR3qvCiO4ra1i4nI+vNgb2ZwyauFxDDVfXtjOnvsLkhROpeh+ MZBx09sIS/bVS54xkij+DRHO4U0i2UGrUpV/TM3qZTrjQK/Iwt95XtcMiH6s+eYSI+ Uoc+M2HyuxVFOFaIQA+GRZ3kSfpbSgBNCd9H52jEGFZDykWTez0/Ro/0azE1S3bp9o 8ECdFYoqATcdGV23F2cGEeo9xM4F/mmtn6FeXQaspeidM9K1gF4Plq+t2SwB33SBWz QI7jrBtDQ9jlr28XR54QAxqybvwJ1UN6f10nf5h6iinv3pgfWgYcBOUlBuFhNlJruE jKYHsNWBBf1lw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43A77D5B149; Mon, 28 Oct 2024 20:25:27 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Mon, 28 Oct 2024 21:24:44 +0100 Subject: [PATCH v4 02/16] net: driver: stmmac: Extend CSR calc support Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241028-upstream_s32cc_gmac-v4-2-03618f10e3e2@oss.nxp.com> References: <20241028-upstream_s32cc_gmac-v4-0-03618f10e3e2@oss.nxp.com> In-Reply-To: <20241028-upstream_s32cc_gmac-v4-0-03618f10e3e2@oss.nxp.com> To: Maxime Coquelin , Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vinod Koul , Richard Cochran , Andrew Lunn , Heiner Kallweit , Russell King , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Emil Renner Berthing , Minda Chen , Nicolas Ferre , Claudiu Beznea , Iyappan Subramanian , Keyur Chudgar , Quan Nguyen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Giuseppe Cavallaro Cc: linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, NXP S32 Linux Team , "Jan Petrous (OSS)" , Jacob Keller X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1730147124; l=2225; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=KCikXBvga2oq/pWon5eW8eJjp8QFlxmOB2nCnbje1+E=; b=SGGNw/CNGfDX9F/CKENWwskdnN4MUmkqyMd8shB0xX+pYitRmj6H89hGhdPvF0LcezEWcRcxR t+6JqSFxz5EDHY3+6TzTuRF0sUxsilEdS2PixMGSSr4yvzOjW9xW8BG X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" Add support for CSR clock range up to 800 MHz. Signed-off-by: Jan Petrous (OSS) Reviewed-by: Jacob Keller --- drivers/net/ethernet/stmicro/stmmac/common.h | 2 ++ drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 4 ++++ include/linux/stmmac.h | 2 ++ 3 files changed, 8 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h index 684489156dce..e364cf99d1ff 100644 --- a/drivers/net/ethernet/stmicro/stmmac/common.h +++ b/drivers/net/ethernet/stmicro/stmmac/common.h @@ -257,6 +257,8 @@ struct stmmac_safety_stats { #define CSR_F_150M 150000000 #define CSR_F_250M 250000000 #define CSR_F_300M 300000000 +#define CSR_F_500M 500000000 +#define CSR_F_800M 800000000 #define MAC_CSR_H_FRQ_MASK 0x20 diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index d3895d7eecfc..f9cab62cfde9 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -324,6 +324,10 @@ static void stmmac_clk_csr_set(struct stmmac_priv *priv) priv->clk_csr = STMMAC_CSR_150_250M; else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M)) priv->clk_csr = STMMAC_CSR_250_300M; + else if ((clk_rate >= CSR_F_300M) && (clk_rate < CSR_F_500M)) + priv->clk_csr = STMMAC_CSR_300_500M; + else if ((clk_rate >= CSR_F_500M) && (clk_rate < CSR_F_800M)) + priv->clk_csr = STMMAC_CSR_500_800M; } if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I) { diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index 75cbfb576358..865d0fe26f98 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -34,6 +34,8 @@ #define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */ #define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */ #define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/124 */ +#define STMMAC_CSR_300_500M 0x6 /* MDC = clk_scr_i/204 */ +#define STMMAC_CSR_500_800M 0x7 /* MDC = clk_scr_i/324 */ /* MTL algorithms identifiers */ #define MTL_TX_ALGORITHM_WRR 0x0