Message ID | 20241101030902.579789-5-quic_qianyu@quicinc.com |
---|---|
State | Accepted |
Commit | fba6045161d686adc102b6ef71b2fd1e5f90a616 |
Headers | show |
Series | Add support for PCIe3 on x1e80100 | expand |
On Thu, Oct 31, 2024 at 08:09:01PM -0700, Qiang Yu wrote: > Currently, the cfg_1_9_0 which is being used for X1E80100 doesn't disable > ASPM L0s. However, hardware team recommends to disable L0s as the PHY init > sequence is not tuned support L0s. Hence reuse cfg_sc8280xp for X1E80100. > > Note that the config_sid() callback is not present in cfg_sc8280xp, don't > concern about this because config_sid() callback is originally a no-op > for X1E80100. > > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> This one should also have been marked for backporting: Fixes: 6d0c39324c5f ("PCI: qcom: Add X1E80100 PCIe support") Cc: stable@vger.kernel.org # 6.9 Looks much better now either way: Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Hello, [...] > This one should also have been marked for backporting: > > Fixes: 6d0c39324c5f ("PCI: qcom: Add X1E80100 PCIe support") > Cc: stable@vger.kernel.org # 6.9 Added. > Looks much better now either way: > > Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Also added. Thank you! Krzysztof
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 52e3d71028d8..16af237663ec 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1853,7 +1853,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 }, - { .compatible = "qcom,pcie-x1e80100", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-x1e80100", .data = &cfg_sc8280xp }, { } };