@@ -50,30 +50,38 @@ properties:
maxItems: 1
clocks:
+ minItems: 5
items:
- description: AHB clock to enable register access
- description: Display Port AUX clock
- description: Display Port Link clock
- description: Link interface clock between DP and PHY
- description: Display Port stream 0 Pixel clock
+ - description: Display Port stream 1 Pixel clock
clock-names:
+ minItems: 5
items:
- const: core_iface
- const: core_aux
- const: ctrl_link
- const: ctrl_link_iface
- const: stream_pixel
+ - const: stream_1_pixel
assigned-clocks:
+ minItems: 2
items:
- description: link clock source
- description: stream 0 pixel clock source
+ - description: stream 1 pixel clock source
assigned-clock-parents:
+ minItems: 2
items:
- description: Link clock PLL output provided by PHY block
- description: Stream 0 pixel clock PLL output provided by PHY block
+ - description: Stream 1 pixel clock PLL output provided by PHY block
phys:
maxItems: 1
@@ -175,6 +183,30 @@ allOf:
required:
- "#sound-dai-cells"
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sa8775p-dp
+
+ then:
+ properties:
+ clocks:
+ maxItems: 6
+ clock-names:
+ items:
+ - const: core_iface
+ - const: core_aux
+ - const: ctrl_link
+ - const: ctrl_link_iface
+ - const: stream_pixel
+ - const: stream_1_pixel
+ assigned-clocks:
+ maxItems: 3
+ assigned-clock-parents:
+ maxItems: 3
+
additionalProperties: false
examples:
@@ -177,16 +177,19 @@ examples:
<&dispcc_dptx0_aux_clk>,
<&dispcc_dptx0_link_clk>,
<&dispcc_dptx0_link_intf_clk>,
- <&dispcc_dptx0_pixel0_clk>;
+ <&dispcc_dptx0_pixel0_clk>,
+ <&dispcc_dptx0_pixel1_clk>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
+ <&dispcc_mdss_dptx0_pixel1_clk_src>,
<&dispcc_mdss_dptx0_pixel0_clk_src>;
- assigned-clock-parents = <&mdss0_edp_phy 0>, <&mdss0_edp_phy 1>;
+ assigned-clock-parents = <&mdss0_edp_phy 0>, <&mdss0_edp_phy 1>, <&mdss0_edp_phy 1>;
phys = <&mdss0_edp_phy>;
phy-names = "dp";
On some chipsets the display port controller can support more than one pixel stream (multi-stream transport). To support MST on such chipsets, add the binding for stream 1 pixel clock for display port controller. Since this mode is not supported on all chipsets, add exception rules and min/max items to clearly mark which chipsets support only SST mode (single stream) and which ones support MST. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> --- .../bindings/display/msm/dp-controller.yaml | 32 ++++++++++++++++++++++ .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 9 ++++-- 2 files changed, 38 insertions(+), 3 deletions(-)