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Fri, 6 Dec 2024 04:32:49 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 5 Dec 2024 20:32:49 -0800 From: Abhinav Kumar Date: Thu, 5 Dec 2024 20:32:15 -0800 Subject: [PATCH 44/45] arm64: dts: qcom: add mst support for pixel stream clk for DP0 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241205-dp_mst-v1-44-f8618d42a99a@quicinc.com> References: <20241205-dp_mst-v1-0-f8618d42a99a@quicinc.com> In-Reply-To: <20241205-dp_mst-v1-0-f8618d42a99a@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" , Stephen Boyd , "Chandan Uddaraju" , Guenter Roeck , Kuogee Hsieh , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Vara Reddy , Rob Clark , Tanmay Shah , , , , , , Jessica Zhang , Laurent Pinchart , Abhinav Kumar , Yongxing Mou X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733459543; l=1726; i=quic_abhinavk@quicinc.com; s=20240509; h=from:subject:message-id; bh=un4hA9ddN0lRnZFIY2HnxtENaoFat7W87QwL8lcEOQ8=; b=QPmvyp/XqLohhcgzKVLPSHjlJ6E8fvh5zu+HjvtvJBzaKLvWpXvbfCgq/BlQWVaLg0cKopi7z A6OL9ioks/vAP5u2Hn18Sv3E026aBWiqyoc/Od7t3q5vgylUOcuIA6Z X-Developer-Key: i=quic_abhinavk@quicinc.com; a=ed25519; pk=SD3D8dOKDDh6BoX3jEYjsHrTFwuIK8+o0cLPgQok9ys= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ArVTcdMw8R4-Ihq4rmiDnIBXKj2jsF2j X-Proofpoint-ORIG-GUID: ArVTcdMw8R4-Ihq4rmiDnIBXKj2jsF2j X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 spamscore=0 bulkscore=0 priorityscore=1501 mlxscore=0 impostorscore=0 suspectscore=0 adultscore=0 malwarescore=0 clxscore=1015 mlxlogscore=811 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412060030 From: Yongxing Mou Populate the pixel clock for stream 1 for DP0 for sa8775p DP controller. Signed-off-by: Yongxing Mou Signed-off-by: Abhinav Kumar --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 0dbaa17e5e3f06c61b2aa777e45b73a48e50e66b..0150ce27b98e9894fa9ee6cccd020528d716f543 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3944,16 +3944,20 @@ mdss0_dp0: displayport-controller@af54000 { <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; - assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>; + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>, <&mdss0_dp0_phy 1>; phys = <&mdss0_dp0_phy>; + phy-names = "dp"; operating-points-v2 = <&dp_opp_table>;