From patchwork Thu Dec 12 04:16:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 849816 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D70D1632DE; Thu, 12 Dec 2024 04:17:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733977037; cv=none; b=Tx7gZJIpP3MGT5r2ADnMWXIVZX+p7eXPZmMWpZaGSEKW23Gxa5JpyAVn7MVVYuFWjmUOGTwu9PnGY5ASZD/TI/ccpgXcAbKTBO/R1HKylUNbJr7pS67PzMQx1dTfnP38O8faj+T2sPIha6bRkFoYhYeLG09ygaQg/kMxoDH1VVQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733977037; c=relaxed/simple; bh=Y38oRl/+usbXDzfKZRv19wmb1/Q6MGGo7BG+ToPY02k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jjUWbUawF7bVczVby2/4OL06BRLYRg6yFkr4k3DldC7UtQBXApo1/BK8CkSGEa7sN/05PH8KmoK51kt4zPVA/AeeddREUPGzMbFNPXVgshCDjydSWetuafPfLGWDI5f2nSL6bkTNO3XihXcI2F6tj3NcswmG1aMyfwZAD04gJJM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=V0Z7i//Z; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="V0Z7i//Z" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4BBHD9nE003400; Thu, 12 Dec 2024 04:17:09 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= hIOn6UVOqtXOXdBDdbSbGgEReDVYXXfxopwam8gofTA=; b=V0Z7i//ZsfR2x9/w NqsSmPdKAibHqmZZPF0F2A+25ca/uU1UqTtivs+LCLJ8F9BAgPDOoX8nFcpkDe0A XQm0/ElrcEpRgrGAUzQQO/CRAKIMscuf9BT9NiLauxt41wsu/tpaFHNlPqQ56b6a lbYuqAXmqoTSRIJUS8S8tY5/LaU+Td2+RD9HWHAH6EUbFhgEhTP30gvKFUDqU0TF q7qGf/FYzQaYUbNnlTtVg6es1NmpSE7RtsG5Mw7NqdtRrSalVHccqVe+lp0CmF+r ldawozBK1p3YGPLceVXOGIKo7WGyg4SIlKS8Pf1JyEZuUA7clNhblIK0DcgwK6rx gokVUw== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43ee3nf76p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Dec 2024 04:17:09 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BC4H88u020694 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Dec 2024 04:17:08 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Dec 2024 20:17:03 -0800 From: Md Sadre Alam To: , , , , , , , , , , , CC: , , , Subject: [PATCH v5 02/12] dmaengine: add DMA_PREP_LOCK and DMA_PREP_UNLOCK flag Date: Thu, 12 Dec 2024 09:46:29 +0530 Message-ID: <20241212041639.4109039-3-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241212041639.4109039-1-quic_mdalam@quicinc.com> References: <20241212041639.4109039-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 9Hbi3bZTKiQsPLxrc4PBmXxmlqWK48MB X-Proofpoint-ORIG-GUID: 9Hbi3bZTKiQsPLxrc4PBmXxmlqWK48MB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 malwarescore=0 spamscore=0 priorityscore=1501 mlxscore=0 impostorscore=0 mlxlogscore=999 lowpriorityscore=0 adultscore=0 clxscore=1011 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412120027 Add lock and unlock flag support on command descriptor. Once lock set in requester pipe, then the bam controller will lock all others pipe and process the request only from requester pipe. Unlocking only can be performed from the same pipe. If DMA_PREP_LOCK flag passed in command descriptor then requester of this transaction wanted to lock the BAM controller for this transaction so BAM driver should set LOCK bit for the HW descriptor. If DMA_PREP_UNLOCK flag passed in command descriptor then requester of this transaction wanted to unlock the BAM controller.so BAM driver should set UNLOCK bit for the HW descriptor. BAM IP version 1.4.0 and above only supports this LOCK/UNLOCK feature. Signed-off-by: Md Sadre Alam --- Change in [v5] * Added DMA_PREP_LOCK and DMA_PREP_UNLOCK flag support Change in [v4] * This patch was not included in v4 Change in [v3] * This patch was not included in v3 Change in [v2] * This patch was not included in v2 Change in [v1] * This patch was not included in v1 Documentation/driver-api/dmaengine/provider.rst | 15 +++++++++++++++ include/linux/dmaengine.h | 6 ++++++ 2 files changed, 21 insertions(+) diff --git a/Documentation/driver-api/dmaengine/provider.rst b/Documentation/driver-api/dmaengine/provider.rst index 3085f8b460fa..5f30c20f94f3 100644 --- a/Documentation/driver-api/dmaengine/provider.rst +++ b/Documentation/driver-api/dmaengine/provider.rst @@ -628,6 +628,21 @@ DMA_CTRL_REUSE - This flag is only supported if the channel reports the DMA_LOAD_EOT capability. +- DMA_PREP_LOCK + + - If set, the BAM will lock all other pipes not related to the current + pipe group, and keep handling the current pipe only. + + - All pipes not within this group will be locked by this pipe upon lock + event. + + - only pipes which are in the same group and relate to the same Environment + Execution(EE) will not be locked by a certain pipe. + +- DMA_PREP_UNLOCK + + - If set, BAM will release all locked pipes + General Design Notes ==================== diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 346251bf1026..8ebd43a998a7 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -200,6 +200,10 @@ struct dma_vec { * transaction is marked with DMA_PREP_REPEAT will cause the new transaction * to never be processed and stay in the issued queue forever. The flag is * ignored if the previous transaction is not a repeated transaction. + * @DMA_PREP_LOCK: tell the driver that there is a lock bit set on command + * descriptor. + * @DMA_PREP_UNLOCK: tell the driver that there is a un-lock bit set on command + * descriptor. */ enum dma_ctrl_flags { DMA_PREP_INTERRUPT = (1 << 0), @@ -212,6 +216,8 @@ enum dma_ctrl_flags { DMA_PREP_CMD = (1 << 7), DMA_PREP_REPEAT = (1 << 8), DMA_PREP_LOAD_EOT = (1 << 9), + DMA_PREP_LOCK = (1 << 10), + DMA_PREP_UNLOCK = (1 << 11), }; /**