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Fri, 13 Dec 2024 10:36:45 GMT Received: from [10.213.111.143] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 13 Dec 2024 02:36:38 -0800 From: Akhil P Oommen Date: Fri, 13 Dec 2024 16:05:46 +0530 Subject: [PATCH v2 4/4] arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241213-qcs615-gpu-dt-v2-4-6606c64f03b5@quicinc.com> References: <20241213-qcs615-gpu-dt-v2-0-6606c64f03b5@quicinc.com> In-Reply-To: <20241213-qcs615-gpu-dt-v2-0-6606c64f03b5@quicinc.com> To: Rob Clark , Sean Paul , "Konrad Dybcio" , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Bjorn Andersson" CC: , , , , , Akhil P Oommen , <20241104-add_initial_support_for_qcs615-v5-4-9dde8d7b80b0@quicinc.com>, <20241022-qcs615-clock-driver-v4-3-3d716ad0d987@quicinc.com>, <20240924143958.25-2-quic_rlaggysh@quicinc.com>, <20241108-qcs615-mm-clockcontroller-v3-7-7d3b2d235fdf@quicinc.com>, <20241108-qcs615-mm-dt-nodes-v1-1-b2669cac0624@quicinc.com>, <20241122074922.28153-1-quic_qqzhou@quicinc.com>, Jie Zhang X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; 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Signed-off-by: Jie Zhang Signed-off-by: Akhil P Oommen Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index ee6cab3924a6..860a0db1908c 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -202,6 +202,14 @@ &gcc { <&sleep_clk>; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs615/a612_zap.mbn"; +}; + &qupv3_id_0 { status = "okay"; };